Column ADC Circuit Layout for Compact CMOS Image Sensors
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Solution Overview
Problem
The challenge is to design a solid-state image pickup device with analog/digital converters (ADCs) that can be arranged in limited space while performing high-speed AD conversion, as existing CMOS image sensors face constraints due to the large size of column circuits required for ADCs, which hinder efficient data processing and signal conversion.
Innovation Solution
The solution involves holding pixel signal potentials at a node and using capacitors to decrease the potential in a stepwise manner through transistor-controlled voltage switching, allowing for a comparator to determine digital values, thereby simplifying ADC configuration and enabling their placement in compact spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If column circuits including ADCs are arranged in the vertical direction of an image array to enable high-speed AD conversion, then AD conversion speed is improved, but the width of the column circuit becomes twice the pixel pitch which consumes excessive area
Solution Approach 1:
The patent changes the arrangement dimension of ADCs from vertical (column direction) to horizontal (row direction). By arranging ADCs in the horizontal direction along with pixel rows, the circuit width is reduced to match the pixel pitch rather than requiring twice the pixel pitch, thus resolving the area consumption issue while maintaining high-speed conversion capability through parallel processing architecture
Solution Approach 2:
The patent divides the image sensor into multiple independent processing units, each containing pixels and associated ADCs that can operate autonomously. This segmentation allows parallel AD conversion across multiple rows simultaneously, maintaining high conversion speed while reducing the area required for each individual column circuit by distributing the conversion function across multiple horizontal segments
2Productivity
If a large number of pixels are processed by one ADC at typical moving image processing rate of 30 fps, then data processing capacity is improved, but the conversion time per pixel becomes unrealistically short at 3 ns
Solution Approach 1:
The patent segments the single ADC into multiple ADCs distributed across different row circuits. Each ADC processes pixels from its associated row in parallel, dividing the total processing load from 10 million pixels down to manageable segments. This segmentation enables simultaneous conversion across multiple rows, achieving high productivity without requiring impossibly fast individual conversion rates
Solution Approach 2:
The patent implements continuous parallel processing where multiple rows of pixels are converted simultaneously across multiple ADCs. Instead of sequentially processing all pixels through a single ADC, the system maintains continuous useful action by having multiple conversion operations occurring in parallel, effectively multiplying the data processing capacity while keeping individual conversion times realistic
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher-speed AD conversion and reduces power consumption by simplifying the ADC circuit configuration, enabling faster data processing and efficient signal conversion within the limited space constraints.
Implementation Method 1
A plurality of capacitors are capacitively coupled to a node to which a pixel signal outputted through a vertical readout line is held
Implementation Method 2
The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors
Implementation Method 3
A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state
Data Source
AI summary
There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.