Column ADC Delay-Line Counting for High Resolution at Lower Power
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Solution Overview
Problem
Conventional CMOS image sensors face limitations in counting frequency and power consumption due to high resolution requirements, especially with Correlated Double Sampling and High Dynamic Range Imaging, which restrict available counting time and frame rate, and existing solutions complicate layout design and increase power consumption.
Innovation Solution
A column analog-to-digital converter with a local counting method using a local delay circuit that compares triggered and re-triggered delay data from a delay line circuit to enhance counting resolution and perform self-compensation without additional trim circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the counting frequency is increased to improve ADC resolution, then the resolution is improved, but the power consumption increases and the counting time is limited
Solution Approach 1:
The patent segments the counting process into multiple phases using phase-delayed clock signals. Instead of using a single high-frequency clock, the counting is divided into multiple lower-frequency stages, each handling a portion of the counting task. This segmentation allows the system to achieve high-resolution counting without requiring a single high-frequency clock that would consume excessive power.
Solution Approach 2:
The patent employs periodic phase-delayed clock signals to drive the counting process. By using multiple clock phases with deliberate delays between them, the system performs counting operations in a periodic, staggered manner. This approach distributes the counting workload over time, reducing the instantaneous power consumption while maintaining the required counting resolution.
2Measurement precision
If phase delays are added to increase ADC resolution without raising counting frequency, then the resolution is improved, but the layout area and power consumption increase
Solution Approach 1:
The patent merges the phase-delay generation function into the existing clock distribution network by utilizing the inherent propagation delays of the clock tree structure. Instead of adding separate delay circuits or DLL/PLL components, the design leverages the natural timing differences that already exist in the clock distribution paths, thereby achieving phase delays without additional layout area.
Solution Approach 2:
The clock tree structure serves dual purposes: it distributes clock signals to various components while simultaneously providing the phase delays needed for high-resolution counting. The propagation delays inherent in the clock distribution paths are exploited as a resource, allowing the system to generate multiple phase-shifted clock signals without requiring dedicated delay generation circuits.
3Measurement precision
If phase delays are added to increase ADC resolution, then the resolution is improved, but the layout design difficulty increases due to path balance requirements
Solution Approach 1:
Instead of trying to equalize clock path lengths to achieve phase delays (the conventional approach), the patent inverts the strategy by deliberately using the natural path length differences to create the desired phase delays. This approach eliminates the need for complex path balancing while still achieving the required timing relationships for high-resolution counting.
4Measurement precision
If a local delay line circuit is used to generate multiple phases in LSB, then the resolution is improved, but additional trim circuits are required to eliminate PVT variation
Solution Approach 1:
The delay line circuit is designed to automatically compensate for PVT variations by using feedback from the actual delay measurements. The system self-adjusts the phase delays by comparing expected versus actual delay values and correcting accordingly, eliminating the need for external trim circuits while maintaining high counting resolution across process, voltage, and temperature variations.
Data Source
AI summary
A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit triggers a delay line circuit of the counting circuit to generate first delay data according to the comparator output signal, re-triggers the delay line circuit to generate first re-trigger delay data according to a base clock, and compares the first delay data with the first re-trigger delay data to generate a first counting output.