Column-Parallel ADC Difference Counting for Low-Power Image Sensors
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Solution Overview
Problem
Prior art image sensors with column parallel ADC circuits consume significant power due to counters needing to count complete counts independently, especially as image resolution increases.
Innovation Solution
The column parallel ADC circuit design allows counters to only count the difference between analog signals, with digital processing generating digital signals by summing counts, reducing power consumption by avoiding the need to count the entire range of analog signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all counters count independently from start to finish, then each counter generates accurate digital counts, but power consumption increases significantly
Solution Approach 1:
The patent merges the counting operations of multiple column ADCs by having counters share a common ramp signal and compare results. Instead of each counter independently counting from zero to maximum, they share the counting process through the common ramp signal, reducing redundant counting operations and power consumption while maintaining accurate digital count generation for each column.
2Measurement precision
If image resolution is increased, then image quality improves, but power consumption increases due to more counters operating independently
Solution Approach 1:
The patent implements universality by creating a multi-functional column parallel ADC circuit where multiple column ADCs share common resources including the ramp signal generator and counting mechanism. This allows the system to handle high-resolution images with multiple columns while reducing power consumption through resource sharing, as each column ADC can utilize the same infrastructure rather than requiring dedicated independent counters for each column.
3Measurement precision
If counters count complete counts for all analog signals, then accurate conversion is achieved, but conversion time increases
Solution Approach 1:
The patent applies preliminary action by pre-generating a common ramp signal that all column ADCs can utilize simultaneously. This ramp signal is prepared in advance and shared across all columns, allowing counters to begin their counting operations without waiting for individual signal preparation. This preliminary preparation of the ramp signal enables parallel processing and reduces the overall conversion time while maintaining accurate signal-to-digital conversion.
Data Source
AI summary
A column parallel ADC circuit includes: plural column ADCs and a digital processing circuit. The plural column ADCs generate respective plural digital counts. The plural column ADCs include a first column ADC and a second column ADC. The first column ADC generates a first digital count according to a first analog signal, and the second column ADC generates a second digital count according to a second analog signal. The first digital count is a difference between a first digital signal and a second digital signal. The first and the second digital signals correspond to the first and the second analog signals respectively. The digital processing circuit generates the plural digital signals, wherein the digital processing circuit generates the first digital signal according to the first digital count and the second digital signal.