Column-Parallel ADC Frame Calibration for CMOS Image Sensor Noise
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Solution Overview
Problem
High-resolution CMOS image sensors face challenges with row-wise and column-wise noise, particularly column fixed-pattern noise, which affect sensitivity and output quality, and existing calibration methods often increase power consumption or reduce frame rates.
Innovation Solution
Implementing frame-wise calibration of column-parallel analog-to-digital converters (ADCs) during the vertical blanking interval, with calibration data stored for use during subsequent frame processing, and using differential ADC architectures to mitigate noise sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration is performed for each frame to reduce column-wise noise, then noise reduction improves, but power consumption increases and frame rate decreases
Solution Approach 1:
The patent performs ADC calibration during the vertical blanking interval before the actual frame conversion begins. By completing the calibration operation in advance during the inter-frame period, the system reduces column-wise noise without requiring additional calibration time during frame conversion, thus avoiding frame rate reduction and excessive power consumption.
2Measurement precision
If calibration is performed for each frame to reduce column-wise noise, then noise reduction improves, but frame rate decreases
Solution Approach 1:
The calibration operation is performed preliminarily during the vertical blanking interval that naturally occurs between frames. This timing allows the calibration to complete before the next frame conversion starts, ensuring that full frame rates are maintained while still achieving noise reduction through proper ADC calibration.
3Productivity
If column-parallel ADC architecture is used to achieve high data conversion rates, then productivity improves, but column-wise noise increases
Solution Approach 1:
The system performs ADC calibration during the vertical blanking interval before frame conversion begins. This preliminary calibration compensates for column-wise variations and fixed-pattern noise in the column-parallel ADC architecture, allowing the high data conversion rate capability to be maintained while reducing the harmful column-wise noise effects.
Data Source
AI summary
Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.