Column A/D Converter Using Gray Code to Cut CMOS Sensor Power
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Solution Overview
Problem
Column A/D converters in CMOS image sensors face challenges with high power consumption and limited AD resolution due to the need for frequent clock updates and large burdens on standard clock lines, leading to IR drop and degraded product performance.
Innovation Solution
Implementing a column A/D converter configuration that uses Gray code counters synchronized with a standard clock PLLCK, eliminating low-level bit count operations and reducing power consumption by only inputting the standard clock to Gray code counters, while performing ripple count operations with high-level side bits, and incorporating a bit inconsistency prevention circuit to maintain temporal resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low-level bit count operations are performed for each column in conventional ADCs, then AD conversion can be completed, but power consumption increases and standard clock lines become overloaded
Solution Approach 1:
The patent segments the counting operation into two distinct parts: low-level bits are latched using comparator outputs, while only high-level bits perform ripple count operations. This segmentation eliminates the need for low-level bit counting in each column, thereby reducing power consumption and clock line burden while maintaining AD conversion functionality.
Solution Approach 2:
The patent extracts the low-level bit counting function from the conventional ripple counter operation. By using dedicated latch circuits for low-level bits and only performing ripple counting for high-level bits, the system removes the harmful effect of excessive low-level bit operations that cause power consumption and clock line overloading.
2Measurement precision
If standard clock frequency is increased to improve AD resolution, then measurement precision improves, but IR drop increases and product characteristics deteriorate
Solution Approach 1:
The patent segments the clock usage so that the standard clock PLLCK is only input to Gray code counters for high-level bit generation, rather than being distributed to all column counters. This segmentation reduces the total clock load on the system, allowing higher clock frequencies to be used without excessive IR drop, thereby improving AD resolution while controlling power consumption.
3Productivity
If ripple counters are arranged for all column lines to perform count operations, then AD conversion is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the counter configuration into two types: Gray code counters that receive the standard clock for high-level bit generation, and simple latch circuits for low-level bit storage. This segmentation replaces the conventional approach of using ripple counters for all bits in all columns, thereby reducing device complexity and power consumption while maintaining full AD conversion capability.
Solution Approach 2:
The patent extracts the complex ripple counter operation from the low-level bit processing function. By dedicating simple latch circuits to low-level bits and only using ripple counting for high-level bits, the system removes unnecessary complexity from the majority of the counting operation while preserving AD conversion functionality.
Data Source
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AI summary
A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.