Column A/D Converter Layout for Fast High-Resolution Imaging
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Solution Overview
Problem
In solid-state imaging devices, the A/D conversion of high-order bits using successive approximation and low-order bits using single slope methods faces challenges in maintaining a fixed relationship between the reference signal and ramp signal, leading to inefficiencies in bitrate and frame rate due to voltage mismatches and excessive conversion time.
Innovation Solution
A solid-state imaging device with A/D converters that include first and second comparators, performing binary search to refine the analog signal range and generating high-order and low-order digital signals, respectively, while linking the reference and ramp signals to maintain a fixed relationship, enabling high-speed and high-resolution A/D conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the voltage of reference signal Vref is increased to match a larger range of ramp signal Vrmp, then the A/D conversion range is extended, but the conversion accuracy deteriorates because a region that cannot be A/D converted occurs during SS conversion
Solution Approach 1:
The A/D conversion process is divided into two distinct stages: SAR conversion for high-order bits and SS conversion for low-order bits. Each stage operates with optimized voltage ranges, allowing the system to achieve both wide overall conversion range and high accuracy in each segment without the trade-off present in single-stage conversion.
2Adaptability or versatility
If the range of the change in ramp signal Vrmp is increased to cover a wider voltage range, then the A/D conversion range is extended, but the conversion time increases making the frame rate lower
Solution Approach 1:
The conversion process is segmented into SAR conversion (for high-order bits with faster convergence) and SS conversion (for low-order bits). This segmentation allows the system to achieve wide conversion range while maintaining high frame rate because the SAR stage quickly narrows down the voltage range before the SS stage performs fine-grained conversion.
Solution Approach 2:
The SAR conversion performs a preliminary coarse conversion that quickly identifies the high-order bits and narrows down the voltage range. This preliminary action prepares the signal for the subsequent SS conversion, reducing the time required for the final low-order bit conversion and thereby increasing overall frame rate.
3Measurement precision
If different A/D conversion methods are used for high-order bits and low-order bits, then high-speed and high-resolution conversion is achieved, but the device complexity increases due to multiple comparators and conversion stages
Solution Approach 1:
The A/D converter is segmented into two functional blocks: a SAR conversion unit with first comparator for high-order bits, and an SS conversion unit with second comparator for low-order bits. This segmentation achieves high resolution (12-bit or higher) by combining the strengths of both methods while keeping each block relatively simple and modular.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for high-speed and high-resolution A/D conversion at high frame rates by maintaining an optimal relationship between the reference and ramp signals, enhancing imaging quality and efficiency.
Implementation Method 1
a plurality of pixel cells arranged in an X-direction and a Y-direction, the plurality of pixels cells each including a photoelectric converter that converts an optical signal to an electrical signal
Data Source
AI summary
A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.