Column ADC Latch Architecture for Continuous CMOS Image Sensing
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in maintaining high image quality and processing speed while preventing an increase in circuit size, especially when the number of pixels, frame rate, or conversion bit width is increased, due to the need for multiple latch circuits and increased signal lines and power consumption.
Innovation Solution
The implementation of a solid-state imaging device with a matrix of sensing elements and column analog-to-digital conversion circuits, including comparators, column counters, and latch units that allow for efficient storage and reproduction of latch clock signals, enabling continuous AD conversion operations without resetting count values and reducing the number of latch circuits required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple latch circuits are provided for continuous AD conversion operations, then processing speed and conversion accuracy are improved, but circuit size increases
Solution Approach 1:
The patent merges the functions of multiple latch circuits into a single latch circuit by implementing a column counter that automatically retains and accumulates count values across multiple AD conversion operations. This consolidation eliminates the need for separate latch circuits for each operation, thereby maintaining high processing speed while reducing circuit size.
Solution Approach 2:
The column counter is designed to serve multiple functions: it performs AD conversion counting, automatically retains count values across operations, and accumulates results for digital vertical pixel addition. This multi-functionality replaces what would traditionally require multiple specialized latch circuits, achieving both speed and space efficiency.
2Measurement precision
If the number of latch circuits is increased for higher conversion accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the precision-retention functions of multiple latch circuits into a single latch circuit working in conjunction with a column counter. The column counter automatically preserves count values with high precision across multiple operations, achieving the same accuracy as multiple latch circuits would provide, but with reduced device complexity.
3Productivity
If more signal lines are added for multiple latch operations, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple signal line functions into a reduced set of lines by implementing automatic count value retention in the column counter. This eliminates the need for additional signal lines that would be required to control multiple latch circuits, thereby maintaining enhanced processing capability while reducing power consumption associated with driving those extra lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high image quality and high-speed processing without increasing circuit size, even with increased pixel counts and bit widths, by efficiently managing latch operations and reducing the number of latch circuits needed.
Implementation Method 1
a plurality of sensing elements arranged in a matrix format for measuring physical quantities with respect to visible rays, electromagnetic waves, alpha rays, beta rays, etc.
Data Source
AI summary
In a solid-state imaging device which includes column analog-to-digital conversion circuits (ADCs) for converting pixel signals output from pixels into digital signals, each of the column ADCs includes a comparator which outputs a result of voltage comparison (comparison result signal) between the voltage of the pixel signal and an analog ramp voltage; a column counter which counts a column counter clock signal, which is either a clock signal or a phase-shifted clock signal, and stores a value represented by upper bits of a count value at a time of change in the comparison result signal; and a first latch unit which stores a value represented by lower bits of the count value. A second latch unit stores the value stored in the first latch unit.