Column ADC Local Counting for Higher Resolution at Lower Power
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in increasing ADC resolution without raising counting frequency, leading to limited frame rates and high power consumption, particularly due to the limitations of single-slope ADCs and phase delays, which also complicate layout design and require additional trim circuits.
Innovation Solution
A column analog-to-digital converter with a local counting method that uses a comparator output signal to generate a local clock, allowing for increased resolution and self-compensation without the need for trim circuits, by combining counting outputs from both the base clock and local clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the counting frequency is increased to raise ADC resolution, then the resolution is improved, but the power consumption increases and the frame rate is limited
Solution Approach 1:
The patent divides the counting process into two independent segments: a first counter counts the base clock cycles, and a second counter counts the local clock cycles generated by the VCO. This segmentation allows the system to achieve high resolution through the combination of both counters without requiring a single high-frequency counter, thereby reducing power consumption while maintaining high ADC resolution.
2Measurement precision
If phase delays are added to increase ADC resolution, then the resolution is improved, but the layout area increases and the layout design becomes more difficult
Solution Approach 1:
The patent replaces the mechanical/physical approach of using phase delay circuits (DLL/PLL) with a digital signal processing approach. By using a VCO to generate a local clock and combining counts from two independent counters, the system achieves the same resolution enhancement without the complex phase delay circuitry, thereby simplifying layout design and reducing layout area.
3Measurement precision
If a local delay line is used to generate multiple phases, then the resolution is improved, but additional trim circuits are required to eliminate PVT variation
Solution Approach 1:
The patent employs a self-calibration mechanism where the system automatically compensates for PVT variations without requiring external trim circuits. The VCO-based local clock generation and the dual-counter architecture inherently adapt to process, voltage, and temperature variations, eliminating the need for additional trim circuits and reducing overall circuit complexity.
4Measurement precision
If the counting time is increased to raise ADC resolution, then the resolution is improved, but the frame rate is limited
Solution Approach 1:
The patent introduces dynamic clock generation by using a VCO to produce a local clock whose frequency is derived from the base clock. This dynamic approach allows the system to perform high-resolution conversion within the same frame time by utilizing the relationship between base clock counts and local clock counts, thereby maintaining high frame rates while achieving high ADC resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ADC resolution while reducing system complexity and power consumption, effectively addressing the limitations of conventional technologies by enabling higher resolution without increasing counting frequency or requiring additional trim circuits.
Implementation Method 1
A voltage-controlled oscillator of the counting circuit generates a local clock according to the base clock and the comparator output signal
Data Source
AI summary
A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.