Column ADC Single-Ended Comparators for Low-Noise Image Sensors
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Solution Overview
Problem
Conventional ramp analog-to-digital converters (ADCs) used in image sensors suffer from high noise levels and elevated power consumption due to the use of differential comparators.
Innovation Solution
The implementation of low noise single-ended comparison stages in the analog-to-digital converter circuitry, which reduces power consumption and minimizes noise levels by using single-ended voltage comparison circuits instead of differential comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If differential comparators are used in ramp ADCs, then high bit resolution can be achieved, but noise levels and power consumption increase
Solution Approach 1:
The patent changes the operational parameters of the comparator by using single-ended comparison instead of differential comparison. This parameter change modifies the comparison mechanism to use a single input reference voltage rather than differential voltages, thereby reducing noise generation while maintaining the ability to achieve high bit resolution through the ramp ADC architecture.
Solution Approach 2:
The patent extracts the noise-generating differential structure from the comparator circuit and replaces it with a single-ended comparison stage. By removing the differential pair configuration that inherently generates higher noise, the design achieves low noise operation while still providing sufficient comparison accuracy for high-resolution ADC conversion.
2Measurement precision
If differential comparators are used in ramp ADCs, then high bit resolution can be achieved, but power consumption increases
Solution Approach 1:
The patent changes the power consumption parameter by transitioning from differential comparator operation to single-ended comparison. This parameter change reduces the number of active transistors and current paths in the comparison stage, thereby lowering power consumption while maintaining the precision required for high bit resolution through the ramp ADC's counting mechanism.
Solution Approach 2:
The patent extracts the power-intensive differential amplifier structure from the comparator and replaces it with a simpler single-ended comparison circuit. This removal of the differential configuration eliminates redundant current paths and reduces overall power consumption while preserving the essential comparison function needed for high-resolution conversion.
3Object-generated harmful factors
If single-ended comparison stages are used, then power consumption and noise levels are reduced, but device complexity must be managed
Solution Approach 1:
The patent extracts the complex differential comparator structure and replaces it with a simpler single-ended comparison stage. This extraction of the differential configuration reduces circuit complexity by removing redundant transistors, resistors, and biasing circuits, while the resulting simpler circuit inherently generates less noise due to fewer active elements and smaller parasitic capacitances.
Data Source
AI summary
An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.