Column-Parallel ADC With Matched Ramp Line for Dental X-Ray Sensors
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Solution Overview
Problem
Conventional column parallel ADCs are inadequate for dental X-ray CMOS image sensors due to limited input voltage window, low resolution, high noise, and power consumption issues, which prevent their use in digital X-ray imaging systems.
Innovation Solution
A 12-bit single-slope column parallel ADC configuration is implemented, where each column of the CMOS pixel array is directly connected to a column-parallel ADC, receiving global ramp signals to match differential inputs and reduce noise, and a matched global ramp line is used to attenuate noise, ensuring operation within a linear range and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional column parallel ADCs are used in CMOS image sensor, then device complexity is reduced and ease of manufacture is improved, but measurement precision is insufficient (only 10 bits resolution) and input voltage window is limited (about 1 Volt or less)
Solution Approach 1:
The pixel array is divided into multiple columns, with each column having its own dedicated single-slope ADC. This segmentation allows each ADC to operate independently with optimized parameters for high-resolution conversion, achieving 12-bit or higher resolution while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent implements dynamic range extension by combining multiple ADC output ranges through differential measurement techniques. The system dynamically adjusts the input voltage window by referencing pixel signals and reset levels to a global ramp line, effectively doubling the input voltage window beyond conventional 1-Volt limitations.
2Area of stationary object
If column parallel ADCs are used with long supply lines, then area is increased to accommodate more pixels, but power consumption increases causing voltage gradient and noise in outputs
Solution Approach 1:
The patent establishes a global ramp line that serves as a common reference potential for all column ADCs across the large sensor area. By referencing all pixel signals and reset levels to this equipotential ramp line rather than local column grounds, the system eliminates voltage gradients caused by IR drops in long supply lines, ensuring consistent output signals across the entire sensor array.
Solution Approach 2:
The global ramp line acts as an intermediary reference signal that mediates between the power distribution network and the ADC inputs. Instead of directly connecting power supplies to each column, the ramp line provides a stable, noise-immune reference that all columns share, isolating the ADCs from power supply noise and voltage drops.
3Reliability
If analog amplifiers and buffers are placed between pixel array and column parallel ADCs, then signal conditioning is improved, but non-ideal circuit paths are introduced increasing noise and complexity
Solution Approach 1:
The patent extracts the signal conditioning function from separate analog amplifiers and buffers and integrates it directly into the column ADC conversion process. By performing the conversion directly at the pixel column output without intermediate analog stages, the system eliminates the noise and non-idealities introduced by separate amplification and buffering circuits while maintaining signal integrity through the direct single-slope conversion architecture.
Data Source
AI summary
An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.