Column ADC Multiphase Latching for Faster Image Sensor Readout
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Solution Overview
Problem
Existing analog-to-digital converters in image sensors face challenges in increasing the frequency of counter code signals to enhance frame rate, pixel density, and image quality while maintaining compatibility with required specifications, as increasing frequency leads to reduced transmission distance and conversion bits.
Innovation Solution
The integration of phase division circuits in column circuits at appropriate intervals, generating high-speed signals by combining counter code signals, allows the semiconductor device to operate at speeds higher than the counter code signal frequency, enabling long-distance and high-load transmission with reduced probability of erroneous counting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the counter code signal is increased to enhance frame rate and sampling speed, then the productivity and speed of the analog-to-digital converter is improved, but the transmission distance is reduced and the probability of erroneous counting increases
Solution Approach 1:
The patent divides the counter code signal transmission into multiple phases (multiphase counter code signal) and introduces local phase division circuits at intervals in the column. This segmentation allows the high-frequency signal to be generated locally rather than transmitted over long distances, resolving the contradiction between high frame rate and transmission reliability.
Solution Approach 2:
The patent introduces phase division circuits as intermediary elements between the global counter and the latch circuits. These intermediary circuits generate high-speed signals locally, acting as mediators that enable high frame rates without requiring long-distance transmission of high-frequency signals, thus maintaining transmission reliability.
2Measurement precision
If the frequency of the counter code signal is increased to enable multiple samplings for reducing noise, then the measurement precision is improved, but the transmission distance is reduced
Solution Approach 1:
The patent segments the column into multiple sections with phase division circuits installed at appropriate intervals. This allows high-frequency signals for multiple sampling to be generated locally in each section, enabling noise reduction through multiple samplings while maintaining long transmission distances across the entire sensor array.
3Measurement precision
If the number of bits of the counter-code signal is increased to improve image quality, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent combines gray code and Johnson counter code into a unified multiphase counter code signal system. This merging approach achieves high-bit precision for improved image quality while using a unified circuit architecture that reduces overall device complexity compared to separate coding systems.
4Speed
If the frequency of the counter code signal is increased to achieve higher execution speed, then the speed is improved, but the transmission distance must be shortened
Solution Approach 1:
The patent segments the column circuit into multiple sections with phase division circuits at intervals, allowing high-speed signal generation to occur locally in each segment. This enables high execution speed throughout the entire device without requiring short transmission distances, as each segment operates independently at high speed.
Solution Approach 2:
The patent transitions from a single global high-frequency clock to a distributed multiphase signal system. By adding the spatial dimension of distributed phase division circuits across the column, the system achieves high execution speed without compromising transmission distance.
Data Source
AI summary
An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.