Column ADC Two-Step Ramp Conversion for Faster CMOS Sensing

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Solution Overview

Problem

Existing imaging devices face a low frame rate due to the increased time required for multiple comparisons in analog-to-digital conversion processes, which hampers the efficiency of converting analog pixel output signals into digital data.

Innovation Solution

The implementation of a column ADC system that operates in two steps: a 'coarse' operational step using a first ramped reference signal to determine the operating point, followed by a 'fine' operational step using a second ramped reference signal that ramps multiple times around the operating point, with a feedback switch control circuit to manage the reference signals and counters for efficient conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple comparisons of the pixel output signal with the ramped reference signal are performed to increase conversion accuracy, then the analog-to-digital conversion precision is improved, but the conversion time increases resulting in low frame rate

Engineering Contradiction:
Improveconversion accuracyVSAvoidframe rate
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the analog-to-digital conversion process into two distinct stages: a coarse conversion stage that quickly determines the most significant bits, and a fine conversion stage that precisely determines the least significant bits. This segmentation allows the system to achieve high conversion accuracy through multiple comparisons while maintaining high frame rate by performing only one quick coarse comparison and one precise fine comparison, rather than requiring many sequential comparisons.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If multiple comparisons are performed to increase conversion accuracy, then the digital data precision is improved, but the time required for conversion increases

Engineering Contradiction:
Improvedigital data precisionVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs a preliminary coarse conversion that quickly establishes the most significant bits of the digital output. This preliminary action provides an initial approximation that narrows down the range for subsequent fine conversion, thereby reducing the total time required to achieve high precision digital data while maintaining accurate conversion results.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a single ramped reference signal is used for conversion, then the conversion process is simple and fast, but the conversion accuracy is limited

Engineering Contradiction:
Improveconversion speedVSAvoidconversion accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent dynamically switches between two different reference signal modes: a first ramped reference signal for coarse conversion and a second ramped reference signal for fine conversion. This dynamic adaptation allows the system to maintain high conversion speed through the efficient coarse stage while achieving high accuracy through the precise fine stage, optimizing both speed and accuracy throughout the conversion process.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8890742B2Column analog-to-digital converter for CMOS sensor
Publication Date: 2014.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8890742B2 patent drawing
  • US8890742B2 patent drawing
  • US8890742B2 patent drawing

AI summary

A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.