Column ADC Signal Attenuation for Faster High-Illuminance Readout
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Solution Overview
Problem
Conventional solid-state imaging elements with column analog-to-digital converters experience slow AD conversion speeds due to increased pixel signal levels at higher illuminance, leading to prolonged comparison result inversion times.
Innovation Solution
A signal processing circuit that includes an attenuation unit to reduce input signals above a threshold, a comparison device to compare the attenuated signal with a varying reference, and a counter to generate digital signals, along with a digital signal processing unit that performs multiplication processing to enhance conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-slope ADC with comparison device and counter is used for each column, then the configuration remains simple, but the AD conversion speed becomes slow when pixel signal level increases at higher illuminance
Solution Approach 1:
The patent applies dynamics by making the ADC configuration adaptable to signal conditions. The system dynamically switches between two ADC modes: single-slope ADC for low signal levels and dual-slope ADC for high signal levels. This dynamic adaptation allows the system to maintain simple configuration when possible while achieving fast conversion speed when needed, resolving the contradiction between simplicity and speed.
Solution Approach 2:
The patent changes the operational parameters of the ADC based on signal characteristics. By detecting the pixel signal level and adjusting the ADC type accordingly, the system optimizes conversion speed for different illuminance conditions. The parameter change from single-slope to dual-slope mode enables the system to handle high signal levels efficiently without sacrificing the simplicity advantage when signal levels are low.
2Quantity of substance
If the pixel signal level increases at higher illuminance, then the signal captures more light information, but the time until comparison result inversion becomes long
Solution Approach 1:
The system dynamically adjusts the ADC operation mode based on the pixel signal level. When high illuminance produces high signal levels that would cause long inversion times, the system switches to dual-slope ADC mode which completes conversion faster. This dynamic response prevents time loss while preserving the ability to capture high light information.
Solution Approach 2:
The patent uses a dummy pixel to generate a dummy signal that copies the timing characteristics of actual pixel signals. This dummy signal is used to control the switching between ADC modes, allowing the system to prepare for and respond to high signal level conditions without waiting for actual pixel data, thereby reducing overall conversion time.
3Speed
If a dual-slope ADC is used to increase AD conversion speed for high signal levels, then the conversion speed improves, but the device complexity increases
Solution Approach 1:
The patent segments the ADC functionality into two distinct modes: single-slope ADC and dual-slope ADC. Each mode is optimized for specific signal level ranges. The system uses a selection mechanism to choose the appropriate mode, avoiding the need to implement both modes simultaneously in the entire system. This segmentation reduces overall complexity while maintaining high conversion speed capability when needed.
Solution Approach 2:
The patent applies different ADC characteristics to different signal level conditions. Instead of using a complex dual-slope ADC for all conditions, the system uses single-slope ADC for low signal levels where simplicity is sufficient, and only employs dual-slope ADC for high signal levels where speed is critical. This local quality approach optimizes the balance between complexity and performance for each operating condition.
Data Source
AI summary
In a digital signal processing circuit that performs AD conversion using a comparison device and a counter, the speed of the AD conversion is increased.An attenuation unit, in a case where the level of an input signal exceeds a predetermined threshold value, attenuates the input signal and outputs it as an output signal. The comparison device compares the output signal with a predetermined reference signal that changes with lapse of time, and outputs the comparison result. The counter counts a count value until the comparison result is inverted and outputs a digital signal indicating the count value. The digital signal processing unit performs multiplication processing on the digital signal.