Column A/D Converter Using Up-Down Counting for Signal Extraction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital (A/D) conversion mechanisms in semiconductor devices, such as CMOS image sensors, face challenges related to circuit size, power consumption, noise, and increased current consumption due to the need for multiple memory systems and signal lines for processing and transferring count results, which complicates the extraction of signal and reset components from pixel signals.
Innovation Solution
A method and converter that perform A/D conversion by comparing a reference signal with both the standard and signal components of an analog signal, using a counter that switches between down-count and up-count modes to directly calculate the difference between these components, eliminating the need for separate memories and dedicated subtractors, thereby reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate memory systems and dedicated subtractors are used to extract signal and reset components, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the memory function and subtraction function into a single counter device. The counter stores the standard component value, and when the signal component is input, it automatically performs the subtraction operation by comparing the combined signal with the stored standard component, eliminating the need for separate memory systems and dedicated subtractors.
Solution Approach 2:
The counter device is designed to perform multiple functions: it acts as both a memory storage device for the standard component and as a subtraction device for extracting the signal component. This multi-functional design reduces the overall number of components needed in the A/D conversion system.
2Measurement precision
If multiple memory systems and signal lines are used for processing and transferring count results, then measurement precision is improved, but use of energy increases
Solution Approach 1:
By merging the memory and subtraction operations into a single counter, the patent reduces the number of active components that consume power. Fewer memory systems and signal lines mean reduced current consumption and lower overall power requirements for the A/D converter.
3Measurement precision
If multiple memory systems and signal lines are used for processing and transferring count results, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functional components (memory systems and subtractors) into a single counter device, thereby reducing device complexity while maintaining the precision needed for component extraction.
4Measurement precision
If conventional A/D conversion mechanisms are used, then signal component extraction is achieved, but loss of time increases due to complex processing
Solution Approach 1:
The counter pre-stores the standard component value before the signal component arrives. When the combined signal is input, the subtraction operation can immediately begin without waiting for separate memory retrieval, thus reducing processing time while maintaining extraction accuracy.
Data Source
AI summary
A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.