Column Address Decoding with Non-Overlapping Clocks for Memory Buffer Selection
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Solution Overview
Problem
Current semiconductor memory access methods face inefficiencies in data retrieval and verification processes, particularly in handling dysfunctional memory locations, which can lead to delays and reduced performance due to the need for complex decoding and remapping circuits.
Innovation Solution
The implementation of a memory access system that utilizes a page buffer coupled with address and decode circuits, including content addressable memory (CAM) for remapping, and selection circuits driven by non-overlapping clocks to efficiently select and verify data from memory cells, thereby addressing the inefficiencies in data access and handling dysfunctional locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex decoding and remapping circuits are used to handle dysfunctional memory locations, then memory access reliability is improved, but device complexity and access time increase
Solution Approach 1:
The address decoding process is segmented into multiple independent stages: initial column address decoding, row address decoding, and verification decoding. Each stage handles specific portions of the address, allowing parallel processing and reducing the complexity of any single decoding circuit while maintaining reliable handling of dysfunctional locations through the verification stage.
Solution Approach 2:
The system performs preliminary decoding of the column address to generate an initial column select signal before full verification is complete. This preliminary action allows the memory system to begin preparing for data access while the verification process continues, reducing overall access time without sacrificing reliability in handling dysfunctional locations.
2Reliability
If complex decoding and remapping circuits are used to handle dysfunctional memory locations, then memory access reliability is improved, but access speed decreases
Solution Approach 1:
The verification process operates periodically with predetermined timing, allowing the system to efficiently batch verification operations rather than processing each address individually. This periodic verification approach maintains reliability for dysfunctional locations while improving overall access speed through optimized timing cycles.
Solution Approach 2:
The system performs preliminary decoding of the column address to generate an initial column select signal before full verification is complete. This preliminary action allows the memory system to begin preparing for data access while the verification process continues, reducing overall access time without sacrificing reliability in handling dysfunctional locations.
3Productivity
If synchronous clock periods are used for decoding and selection, then productivity is improved, but device complexity increases
Solution Approach 1:
The system merges the decoding operation and the buffer selection operation into a single synchronous clock cycle. By combining these operations that were previously sequential into a parallel synchronous process, the system improves productivity without requiring complex multi-stage clock synchronization mechanisms, as both operations share the same clock domain.
Solution Approach 2:
The synchronous clock signal serves multiple functions simultaneously: it drives the address decoding logic, controls the timing of verification signals, and coordinates the buffer selection process. This universal clocking approach improves productivity by synchronizing all operations while avoiding the complexity of multiple independent clock circuits.
Data Source
AI summary
Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time period, and selecting one or more cells of a buffer coupled to a memory array based, at least in part, on the decoded address, during a second time period.