Semiconductor Column Address Circuit Pre-Counting Mechanism
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Solution Overview
Problem
The column address circuit in semiconductor memory devices faces challenges in generating column addresses efficiently, leading to potential errors during high-speed operations due to the use of repair address comparators, which increases the time required for data output and compromises the margin for count operations.
Innovation Solution
The introduction of an internal dummy clock generated by a dummy enable signal before the read enable signal allows for pre-counting of column addresses, ensuring an adequate margin for count operations by synchronizing these addresses with output clocks, thereby reducing the reliance on repair address comparators and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column addresses are sent to a plane through a repair address comparator, then address verification is improved, but the time required for data output increases and margin for count operation is compromised
Solution Approach 1:
The patent applies preliminary action by generating an internal dummy clock in advance using a dummy enable signal that is activated before the read enable signal. This allows the column address circuit to pre-count and generate column addresses before the actual read operation, ensuring adequate margin for count operation and reducing the time required during actual data output while maintaining address verification reliability
2Measurement precision
If column addresses are generated using repair address comparator, then address accuracy is maintained, but high-speed operation margin is compromised
Solution Approach 1:
The patent generates column addresses in advance using a dummy enable signal activated before the read enable signal, allowing the count operation to complete beforehand. This preliminary generation of addresses maintains accuracy through proper synchronization while providing sufficient margin for high-speed operations
3Ease of operation
If column addresses are counted in real-time during read operation, then operational simplicity is maintained, but adequate margin for count operation is compromised
Solution Approach 1:
The patent implements preliminary counting by activating a dummy enable signal before the read enable signal, which triggers the internal dummy clock to generate column addresses in advance. This approach maintains operational simplicity while ensuring adequate margin for count operation by completing the counting process before the actual read operation begins
Data Source
AI summary
The column address circuit of a semiconductor memory device according to an aspect of the present disclosure includes a column address generation circuit configured to generate an internal dummy clock in response to a data output enable signal, generate an internal clock in response to a read enable signal, generate first count addresses in response to the internal dummy clock, and generate normal count addresses in response to the internal clock after the generation of the first count addresses, where the read enable signal is activated later than the data output enable signal, and a column address output circuit configured to store the first count addresses and the normal addresses and to generate column addresses by synchronizing the first count addresses and the normal addresses with output clocks, respectively.