Dynamic Column Address Enable Signal Pulse Width Adjustment
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Solution Overview
Problem
Conventional column address enable signal generation circuits in semiconductor memory devices provide a constant pulse width for the column address selection signal, leading to suboptimal data transmission and reception times between bit lines and local input/output lines, causing timing mismatches and operational failures at varying frequency operations.
Innovation Solution
A semiconductor memory device with a clock period detector, column address enable signal generator, and multiplexing circuit that adjusts the pulse width of the column address enable signal based on the external clock frequency, using a clock period detector to sense the external clock pulse width and a multiplexing circuit to vary the activation intervals of the column access signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant pulse width is provided for the column address selection signal, then the circuit structure is simple, but timing mismatches and operational failures occur at varying frequency operations
Solution Approach 1:
The patent implements dynamic adjustment of the column address enable signal pulse width based on the external clock frequency. The clock frequency detector continuously monitors the external clock frequency, and the pulse width adjustment circuit dynamically modifies the pulse width of the column address enable signal to match the detected frequency, ensuring optimal timing across varying operating conditions.
Solution Approach 2:
The patent changes the pulse width parameter of the column address enable signal based on the external clock frequency. By detecting the external clock frequency and adjusting the pulse width parameter accordingly, the system adapts to different frequency operations, preventing timing mismatches and operational failures while maintaining circuit simplicity through parameter-based adaptation.
2Duration of action of moving object
If the pulse width of the column address enable signal is increased, then data transmission time is sufficient, but the activation interval becomes too long causing timing mismatches at high frequency operations
Solution Approach 1:
The system dynamically adjusts the pulse width of the column address enable signal based on the external clock frequency. At high frequencies, the pulse width is reduced to match the shorter clock period, preventing timing mismatches. At low frequencies, the pulse width is increased to ensure sufficient data transmission time, thus adapting to different operating speeds.
Solution Approach 2:
The pulse width parameter of the column address enable signal is changed according to the external clock frequency. The clock frequency detector monitors the frequency, and the pulse width adjustment circuit modifies the parameter to optimize both data transmission time and operation speed for different frequency conditions.
3Speed
If the pulse width of the column address enable signal is decreased, then operation speed increases, but data transmission and reception time becomes insufficient
Solution Approach 1:
The system dynamically adapts the pulse width of the column address enable signal to the external clock frequency. When operating at high frequencies, the pulse width is decreased to maintain fast operation speed. When operating at low frequencies, the pulse width is increased to ensure sufficient data transmission time, thus dynamically balancing speed and transmission duration.
Solution Approach 2:
The pulse width parameter is adjusted based on the external clock frequency to optimize the balance between operation speed and data transmission time. The clock frequency detector and pulse width adjustment circuit work together to change the parameter appropriately for different operating conditions.
4Device complexity
If a fixed delay time is used in the delay circuit, then the circuit is simple, but the column address enable signal pulse width cannot be adjusted to match external clock frequency
Solution Approach 1:
The delay circuit is enhanced with a pulse width adjustment circuit that dynamically modifies the delay time based on the external clock frequency detected by the clock frequency detector. This dynamic adjustment enables the circuit to adapt to different frequency operations while maintaining relative simplicity through a modular enhancement approach.
Solution Approach 2:
The delay time parameter in the delay circuit is adjusted based on the external clock frequency. The clock frequency detector monitors the frequency, and the pulse width adjustment circuit changes the delay time parameter accordingly, enabling frequency adaptability while keeping the base circuit structure simple.
Data Source
AI summary
A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width corresponding to that of the external clock. The column address enable signal generator generates a column address enable signal activated in response to a column access signal. The multiplexing circuit multiplexes points of time of inactivation of the column access signal in response to the detected signal outputted from the clock period detector.