Column Address Segmentation for Electronic Registration Buffer Reduction

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Solution Overview

Problem

Electronic registration systems in high-speed, high-volume document reproduction require large and costly memory buffers to correct beam scan trajectory distortions such as skew and bow, which are expensive and space-constrained.

Innovation Solution

A method that reduces the size of the memory buffer by determining and storing total skew errors for each pixel location in a spatially mapped array, allowing for electronic registration correction with a reduced buffer size, specifically by a factor of 2n-1, where n is the number of column address segments, and performing corrections at various upstream locations in the image path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If large memory buffers are used to store image data for electronic registration correction, then beam scan trajectory distortion correction capability is improved, but system cost and space requirements increase

Engineering Contradiction:
Improvebeam scan trajectory distortion correctionVSAvoidmemory buffer size
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent divides the image data into multiple scanline buffers organized in a hierarchical structure with different buffer levels. Each buffer level stores a portion of the scanlines needed for correction, allowing the system to process and correct trajectory distortions in segments rather than requiring all data in a single large buffer. This segmentation reduces the peak memory buffer size requirement while maintaining correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary calculations of the distortion correction parameters (such as skew and bow coefficients) before the actual image correction process. By pre-computing the correction data and storing it in compact form, the system reduces the amount of memory needed during the correction phase, as the correction can be applied using these pre-calculated parameters rather than storing and manipulating large amounts of raw image data.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If high-speed memory buffers are used to maintain high reproduction speed, then productivity is improved, but system cost increases

Engineering Contradiction:
Improvereproduction speedVSAvoidhigh-speed buffer quantity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements a dynamic buffer management system where the allocation and usage of memory buffers adapts to the current processing requirements. The system dynamically adjusts which buffers are active, how many scanlines are buffered at each level, and the flow of data through the correction pipeline based on the detected distortion characteristics and current processing stage. This dynamic approach allows high-speed processing with minimized buffer requirements by avoiding allocation of buffers that are not currently needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8331738B2Reducing buffer size requirements in an electronic registration system
Publication Date: 2012.12.11 XEROX CORP
  • US8331738B2 patent drawing
  • US8331738B2 patent drawing
  • US8331738B2 patent drawing

AI summary

What is disclosed is a novel system and method for reducing a size of a memory buffer used by an electronic registration correction system performing an electronic registration correction on a digital image. The present method uses column address segmentation to identify blocks of scanlines within a spatially mapped array of image pixels comprising a digital image. Advantageously, the present system and method reduces scanline buffer memory by a factor of 2n-1, where n is the number of column address segments. Buffering can be performed at almost any upstream location in the image path. The present method is well suited for high resolution imaging equipment where memory is constrained by design, cost, or space limitations.