Column-Addressable Memory Media Management via Indirection Tables

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Solution Overview

Problem

Existing memory technologies face inefficiencies in matrix operations due to the need to convert between row-major and column-major formats, which increases latency and computational cost, and storing matrices in both formats increases memory usage.

Innovation Solution

A compute device with a memory controller that performs media management using a column-addressable memory architecture, allowing for efficient memory access and indirection operations, such as moving data to different physical memory ranges to avoid wear and optimize access patterns, while maintaining column-wise data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If matrices are stored in both row-major and column-major formats, then matrix operations can be performed without format conversion, but memory usage increases

Engineering Contradiction:
Improvematrix operation speedVSAvoidmemory usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory space is segmented into distinct row-major and column-major storage regions. The system divides matrix data storage into two separate formats, allowing efficient access patterns for both row-wise and column-wise operations without requiring the entire matrix to be stored twice in both formats simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A format conversion buffer or intermediary storage mechanism is introduced to facilitate temporary conversion between row-major and column-major formats during operations. This intermediary allows the system to perform format conversion on-demand rather than maintaining both formats permanently, reducing overall memory requirements while maintaining operational efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If matrices are converted between row-major and column-major formats during operations, then memory usage is reduced, but latency and computational cost increase

Engineering Contradiction:
Improvememory usageVSAvoidoperation latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary format conversion by pre-processing matrix data into both row-major and column-major formats and storing them in separate memory regions. This preliminary action ensures that when matrix operations are executed, the data is already in the required format, eliminating conversion latency during actual operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory allocation and format selection are made dynamic based on the operation requirements. The system can dynamically switch between row-major and column-major access patterns depending on whether row-wise or column-wise operations are being performed, optimizing both speed and memory efficiency adaptively.

Inventive Principle:
Principle #15Dynamics

3Productivity

If column-addressable memory architecture is used, then column-wise access efficiency is improved, but compatibility with row-major operations may be reduced

Engineering Contradiction:
Improvecolumn-wise access speedVSAvoidoperation format compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The memory controller is designed with multi-functional capabilities to handle both column-addressable and row-major access patterns. It implements universal interface logic that can interpret and execute both column-wise and row-wise operation commands, making the column-addressable memory architecture compatible with diverse matrix operation requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system adds a logical addressing dimension layer above the physical column-addressable memory structure. This logical layer provides row-major addressing abstraction, allowing the memory to physically store data in column-addressable format while presenting row-major access semantics to software, thus achieving compatibility across different operation formats.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11573735B2Technologies for media management in column-addressable memory media systems
Publication Date: 2023.02.07 INTEL CORP
  • US11573735B2 patent drawing
  • US11573735B2 patent drawing
  • US11573735B2 patent drawing

AI summary

Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.