Column ALU Signal Extraction for Image Sensor Power Reduction
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Solution Overview
Problem
Current image sensors face challenges in reducing digital power consumption and efficiently processing image and phase detection autofocus signals, often relying on external image signal processors which can increase power usage.
Innovation Solution
The implementation of column arithmetic logic units (ALUs) within the image sensor that locally extract and store phase detection autofocus signals, using correlated double sampling and dual conversion gain processing, along with a shared Gray code generator for parallel analog-to-digital conversion, reduces power consumption by processing signals internally rather than relying on external processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external image signal processors are used to process image and autofocus signals, then signal processing capability is improved, but digital power consumption increases
Solution Approach 1:
The patent merges the image signal processing and phase detection autofocus signal processing functions into a single integrated arithmetic logic unit (ALU) located within the image sensor. This consolidation eliminates the need for separate external processors, reducing the overall power consumption while maintaining full signal processing capability. The ALU processes both image signals from pixel arrays and PDAF signals from dedicated photodiodes through unified correlated double sampling and arithmetic operations.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a shared Gray code generator that facilitates parallel analog-to-digital conversion for both image and PDAF signals. This intermediary component enables efficient signal transformation within the sensor, reducing the need for high-power external processing while maintaining signal integrity and processing speed.
2Adaptability or versatility
If signal processing is performed externally, then processing flexibility is improved, but device complexity increases
Solution Approach 1:
The arithmetic logic unit is designed with universal functionality to handle multiple signal types including image signals from pixel arrays and phase detection autofocus signals from dedicated photodiodes. The ALU performs correlated double sampling, arithmetic operations, and signal extraction for both signal types through the same hardware structure, eliminating the need for separate processing paths and reducing overall system complexity.
Solution Approach 2:
The patent segments the signal processing function into distinct operational phases within the ALU: correlated double sampling stage, arithmetic operation stage, and signal extraction stage. This segmentation allows the same hardware unit to efficiently process different signal types through standardized operational sequences, maintaining flexibility while reducing the need for multiple specialized processors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces digital power consumption and enhances signal processing efficiency by localizing signal processing within the image sensor, improving the handling of image and phase detection autofocus signals while maintaining high performance metrics.
Implementation Method 1
The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light
Data Source
AI summary
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.