Column-Aware Memory Scrambling for Balanced Power and Wear
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Solution Overview
Problem
Existing memory architectures face challenges in adapting column-based I/O operations due to row-based scrambling schemes, leading to inefficient power consumption and uneven wear on bit locations, which are not addressed by existing technologies such as US2009/0323942A1, US2012/0265928A1, US2013/0018934A1, US2016/0321000A1, US2018/0074791A1, US2019/0227808A1, WO2009/088920A1, and US2017/090764A1.
Innovation Solution
Implementing column-aware scrambling and descrambling techniques using a linear function of row and column indices, specifically through a linear-feedback shift register (LFSR) function, allowing simultaneous scrambling and descrambling of data in columns without executing row-based algorithms per entry, thereby optimizing power consumption and wear distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If row-based scrambling schemes are used, then scrambling functionality is provided, but column-based I/O operations become inefficient and power consumption becomes uneven
Solution Approach 1:
The patent applies local quality by making the scrambling scheme adaptive to the specific I/O operation type. Column-aware scrambling detects whether a column-based I/O operation is being performed and applies the appropriate scrambling method (column-based vs. row-based) locally to that operation, rather than universally applying row-based scrambling to all operations.
Solution Approach 2:
The patent implements dynamics by making the scrambling behavior dynamic and context-dependent. The scrambling scheme dynamically switches between row-based and column-based approaches based on the detected operation type, allowing the system to adapt its scrambling strategy in real-time to match the I/O operation being performed.
2Adaptability or versatility
If row-based scrambling schemes are used, then scrambling functionality is provided, but wear distribution on bit locations becomes uneven
Solution Approach 1:
The patent applies local quality by making the scrambling scheme adaptive to the specific I/O operation type. Column-aware scrambling detects whether a column-based I/O operation is being performed and applies the appropriate scrambling method (column-based vs. row-based) locally to that operation, rather than universally applying row-based scrambling to all operations.
Solution Approach 2:
The patent applies parameter changes by modifying the scrambling parameters (scrambler seed, scrambler polynomial) based on the detected operation type. When column-based I/O is detected, the system changes the scrambling parameters to those optimized for column operations, ensuring uniform wear distribution specific to the column access pattern.
3Ease of manufacture
If row-based scrambling schemes are used, then simple scrambling implementation is achieved, but simultaneous column-based scrambling and descrambling is inefficient
Solution Approach 1:
The patent applies segmentation by dividing the scrambling implementation into distinct column-based and row-based pathways. The column-aware scrambling logic segments the operation flow to detect column-based I/O operations and route them through the optimized column scrambling path, which enables simultaneous scrambling and descrambling operations.
Solution Approach 2:
The patent implements dynamics by making the scrambling behavior dynamic and context-dependent. The scrambling scheme dynamically switches between row-based and column-based approaches based on the detected operation type, allowing the system to adapt its scrambling strategy in real-time to match the I/O operation being performed.
Data Source
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AI summary
Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.