Column CDS AD Conversion Circuit for High-Speed Imaging Precision
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Solution Overview
Problem
Existing analog-to-digital (AD) conversion circuits in imaging apparatuses face challenges in accurately converting analog pixel signals to digital data, particularly in high-speed applications like digital still cameras, where achieving precise difference signals between reset and signal levels is crucial for image quality.
Innovation Solution
The proposed AD conversion circuit includes a reference signal generation section, a comparison section, a first count section, a latch section, and a second count section, which generate and compare analog signals to a reference signal, perform count operations, and output digital data corresponding to the difference between the signals, with the latch and second count sections arranged for every column of the pixel array, enabling efficient correlated double sampling (CDS) process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AD conversion circuit processes analog pixel signals at high speed, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The AD conversion circuit is divided into multiple independent column processing sections, each capable of performing CDS and AD conversion simultaneously and independently. This segmentation allows parallel processing of multiple pixel columns, increasing overall conversion speed while maintaining precision in each individual channel through dedicated hardware resources.
Solution Approach 2:
The circuit performs correlated double sampling by preliminarily capturing and storing the reset level signal before the actual pixel signal conversion. The reset level is sampled and stored in a register, then subtracted from the pixel signal in a predetermined period, ensuring that precision correction is completed before final AD conversion, thus maintaining measurement precision at high speeds.
2Device complexity
If the CDS process is performed within the column section, then device complexity is reduced, but manufacturing precision becomes more difficult to ensure
Solution Approach 1:
The column processing section is designed as a universal module that integrates multiple functions including correlated double sampling, AD conversion, and difference signal calculation into a single unified circuit block. This multi-functional design simplifies the overall device architecture by eliminating separate CDS and AD conversion sections, while maintaining manufacturing precision through standardized module design and integration.
Data Source
AI summary
A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.