Column Circuit Pixel Binning Charge Sharing

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Solution Overview

Problem

Conventional pixel binning technologies are limited to specific pixel structures and cannot perform binning operations across different pixel structures, which restricts their adaptability and efficiency in processing increased pixel data from advanced image sensors.

Innovation Solution

A column circuit and binning circuit design that allows for pixel data from multiple pixels to be read and processed across different column lines, enabling binning operations regardless of pixel structure through a three-phase charging and sharing mechanism, using capacitors and current sources to manage data transfer and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional pixel binning technology is used, then binning can be performed on pixel array, but it is limited to using a certain pixel structure

Engineering Contradiction:
Improvepixel structure adaptabilityVSAvoidbinning circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The column read circuit is designed to perform multiple functions: normal data reading from single column lines and binning operations from multiple column lines. The circuit universally handles both conventional pixel structures and various binning configurations through the same hardware, eliminating the need for structure-specific circuit designs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The binning circuit employs dynamic control signals to switch between different operational modes (normal reading mode and binning mode). By dynamically controlling the timing and routing of data from multiple column lines, the circuit adapts its behavior based on the desired operation without requiring physical reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the number of pixels is increased to improve definition, then image quality is improved, but the amount of data to be processed increases

Engineering Contradiction:
Improveimage definitionVSAvoiddata processing efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The circuit merges data from multiple column lines by accumulating charges from different pixel columns into shared readout circuits. This combining operation reduces the total data volume that needs to be processed externally while maintaining the high-definition capability of the sensor array.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The pixel array is segmented into multiple column groups, each with its own readout circuit. This segmentation allows parallel processing of data from different columns, improving overall data processing efficiency while maintaining high pixel counts for improved definition.

Inventive Principle:
Principle #1Segmentation

3Productivity

If binning is performed on pixel array using conventional technology, then data from multiple pixels can be combined, but it requires specific pixel structure

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidpixel structure flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The column read circuit acts as an intermediary between the pixel array and the output, performing binning operations in this intermediate stage rather than requiring specific pixel structures. This mediator approach allows flexible binning of data from any pixel structure without modifying the pixel design itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8759736B2Column circuit and pixel binning circuit for image sensor
Publication Date: 2014.06.24 SK HYNIX INC
  • US8759736B2 patent drawing
  • US8759736B2 patent drawing
  • US8759736B2 patent drawing

AI summary

A column circuit for an image sensor includes a first column read circuit configured to read data of a first column line, and a second column read circuit configured to read data of a second column line, wherein, during a binning mode, data from two or more pixels are outputted through the first column line and stored in the first column read circuit in a first phase, data from two or more pixels are outputted through the second column line and stored in the second column read circuit in a second phase, and charges are shared between the first column read circuit and the second column read circuit in a third phase.