Column Control Circuit Dynamic Delay for Memory Sampling
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in ensuring stable delay times between column selection start and end signals across varying operating frequencies, which affects the accurate sampling of column selection end signals by column selection window signals.
Innovation Solution
A column control circuit is introduced, comprising a delay control circuit and a control signal generation circuit. The delay control circuit generates a column selection end signal with a first delay amount, while the control signal generation circuit generates a target column selection window signal with a second delay amount, ensuring the window signal's active duration covers the end signal's active duration, regardless of operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the column selection end signal is generated with a fixed delay amount, then the circuit design is simple, but the sampling accuracy deteriorates under varying operating frequencies
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable rather than fixed. The delay control circuit dynamically adjusts the delay amount between column selection start and end signals based on operating frequency, ensuring accurate sampling across different frequency conditions while maintaining reasonable circuit complexity through controlled variability.
Solution Approach 2:
The patent changes the parameter of delay amount from a fixed value to a variable parameter that adapts to operating frequency. By allowing the delay amount to change with frequency conditions, the system maintains signal sampling accuracy without requiring overly complex circuitry, resolving the contradiction between simplicity and precision.
2Reliability
If the active duration of the column selection window signal is extended to cover all possible end signal durations, then the sampling reliability is improved, but the time consumption increases
Solution Approach 1:
The patent applies preliminary action by setting the column selection window signal's active duration to cover the maximum possible end signal duration in advance. This ensures that regardless of the actual delay amount, the window signal will be active long enough to sample the end signal reliably, without requiring real-time adjustment or risking time loss.
Data Source
AI summary
Provided are a column control circuit and a memory device. The column control circuit includes a delay control circuit and a control signal generation circuit. The delay control circuit receives a column selection start signal, and generates and outputs a column selection end signal. The column selection end signal has a first delay amount relative to the column selection start signal. The control signal generation circuit receives the column selection start signal, the column selection end signal, and a target bank group selection signal, and generates and outputs a target column selection start signal, a target column selection window signal, and a target column selection end signal. The target column selection window signal has a second delay amount relative to the column selection start signal, the second delay amount is less than or equal to the first delay amount.