Column Decoder Dual-Point Bitline Coupling for Phase-Change Memory
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Solution Overview
Problem
Phase-change memory devices experience voltage drop along selected local bitlines, leading to undesirable asymmetries and irregularities in memory cell behavior due to varying voltages across memory cells connected to the same bitline.
Innovation Solution
A column decoder is designed with top and bottom subcircuits comprising MOSFETs, allowing each main bitline to be coupled to two points of the selected local bitline, thereby reducing voltage drop and ensuring uniform voltage across memory cells by dividing the current equally at these points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single connection point is used between main bitline and local bitline, then device complexity is reduced, but voltage drop across memory cells increases causing asymmetries and irregularities
Solution Approach 1:
The connection between main bitline and local bitline is segmented into two separate connection points instead of a single point. The first connection point connects to a first portion of the local bitline, and the second connection point connects to a second portion of the local bitline. This segmentation allows current to be injected at multiple locations, reducing voltage drop asymmetries and improving uniformity of memory cell behavior across the array.
2Reliability
If current flows through entire local bitline, then all memory cells are addressed, but voltage drop increases causing electrical stress and performance degradation
Solution Approach 1:
A second connection point is introduced as an intermediary between the main bitline and the local bitline. This intermediary connection point, located at a different position than the first connection point, allows current to be injected into the local bitline at multiple locations. This reduces the overall voltage drop along the bitline by distributing the current injection, thereby reducing electrical stress and improving memory cell performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the maximum voltage drop across memory cells, enhancing uniformity and reducing electrical stress, leading to improved performance in both reading and writing operations.
Implementation Method 1
The column decoder is configured to couple each main bitline to two different points of the corresponding selected local bitline
Data Source
AI summary
An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.