Hierarchical Column Decoder Low-Voltage Transistors Memory Array
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Solution Overview
Problem
Existing non-volatile memory devices require high-voltage components for column decoders, leading to a large footprint and performance issues due to the need for high-voltage MOS transistors, which are inefficient for read operations and occupy significant chip area.
Innovation Solution
Implementing a hierarchical column decoding configuration with low-voltage MOS transistors for the first-level decoders within the p-well region and high-voltage MOS transistors only for the last-level decoders outside the p-well region, allowing for a reduced footprint and improved performance by minimizing the number of high-voltage components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage MOS transistors are used for all column decoder stages, then the memory cells can be properly biased during read operations, but the chip area occupied by the decoder increases significantly and read access speed decreases
Solution Approach 1:
The column decoder is divided into multiple hierarchical stages (first-level decoders within p-well regions and second-level decoders outside p-well regions). Only the final stage requires high-voltage capability, while intermediate stages use low-voltage transistors, segmenting the voltage requirements across different decoder levels.
Solution Approach 2:
Different voltage requirements are applied locally to different parts of the decoder system. Low-voltage MOS transistors are used for first-level decoders within p-well regions where high-voltage biasing is not needed for read operations, while high-voltage MOS transistors are used only for second-level decoders outside p-well regions that interface with sense amplifiers.
2Strength
If high-voltage MOS transistors are used for column decoders, then the memory cells can sustain high voltages during program and erase operations, but the read access path speed is reduced and power consumption increases
Solution Approach 1:
The decoder hierarchy segments high-voltage requirements to only the final stage, allowing intermediate stages to operate at lower voltages with faster switching characteristics, thus improving overall read access speed while maintaining high-voltage capability where needed.
Solution Approach 2:
High-voltage transistors are deployed only where absolutely necessary (second-level decoders outside p-well), while low-voltage transistors with superior speed characteristics are used for first-level decoders, creating local optimization of both voltage handling and speed performance.
3Device complexity
If a single-level column decoder is used, then the decoder structure is simpler, but the number of control signals required increases significantly when scaling to large memory arrays
Solution Approach 1:
The column decoding function is segmented into hierarchical levels, where first-level decoders handle local column selection within p-well regions and second-level decoders handle global column routing to sense amplifiers. This segmentation reduces the control signal burden at each individual stage.
Solution Approach 2:
The decoder architecture adds a hierarchical dimension to the decoding process, organizing decoders in multiple levels rather than a single flat level, which enables more efficient control signal management for large memory arrays.
Data Source
AI summary
A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.