Column Decoder Power Gating for DRAM Layout Optimization
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Solution Overview
Problem
Semiconductor memory devices, such as DRAM, face challenges in laying out driver circuits, control circuits, and power supply circuits in limited space, particularly when compensation capacitance is arranged above the driver circuits, making it impossible to place low-resistance power-supply wiring directly above, resulting in increased chip area due to detouring wiring that creates blank areas without transistors.
Innovation Solution
The column decoder is configured with a power gating circuit sandwiched between the control circuit and the driver circuit, allowing compensation capacitance to be placed above the driver circuit, enabling direct low-resistance wiring and optimizing layout by shifting transistors and wiring patterns to minimize area usage and enhance flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If compensation capacitance is arranged above the driver circuits, then layout space is saved, but low-resistance power-supply wiring cannot be placed above the driver circuits, requiring detouring wiring that increases chip area
Solution Approach 1:
The patent introduces a power gating circuit as an intermediate layer between the control circuit and driver circuit, enabling vertical stacking arrangement. This dimensional reorganization allows compensation capacitance to be placed above the driver circuit while maintaining low-resistance power supply paths through the power gating circuit structure, resolving the conflict between space savings and wiring resistance.
2Reliability
If power-supply wiring detours around the compensation capacitance, then power supply is maintained, but blank areas are created where no transistor is arranged, increasing chip area
Solution Approach 1:
The patent merges the power gating function with the driver circuit structure by positioning the power gating circuit between the control circuit and driver circuit. This integration eliminates the need for separate power supply wiring paths and removes blank areas, as the power gating circuit itself forms part of the active transistor arrangement, thereby reducing overall chip area while maintaining power supply continuity.
3Area of stationary object
If driver circuits, control circuit, and power supply circuit are arranged in limited space, then chip area is reduced, but layout flexibility and wiring routing become more difficult
Solution Approach 1:
The patent segments the column decoder into distinct functional blocks: control circuit, power gating circuit, and driver circuit, arranged in a vertical stack. This segmentation allows each component to be optimized independently and simplifies wiring routing by providing clear hierarchical connections, thereby reducing layout complexity while maintaining compact chip area.
Data Source
AI summary
Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.