Column Address Decoder Refresh for Out-of-Range SRAM Addresses
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Solution Overview
Problem
Asynchronous embedded SRAM memory devices face data integrity loss due to lack of scheduled refresh, leading to increased power consumption and access time complexity when handling out-of-range addresses, which requires additional logic for detection and refresh.
Innovation Solution
A programmable column address decoder is implemented to detect and refresh memory blocks for out-of-range addresses, using a PLA configuration that deactivates unnecessary logic for unused addresses, thereby maintaining a complete electrical path and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If out of range detection logic is added to refresh memory blocks for out-of-range addresses, then data integrity is maintained, but device complexity and power consumption increase
Solution Approach 1:
The column address decoder is designed to perform dual functions: normal column decoding for valid addresses and automatic refresh triggering for out-of-range addresses. By making the decoder universal, no separate detection logic is needed, thus maintaining data integrity without increasing device complexity
Solution Approach 2:
The system uses its existing column address decoder to automatically detect and handle out-of-range addresses without requiring external detection logic. The decoder itself serves the refresh function by detecting when its output is invalid and triggering the appropriate refresh operation
2Reliability
If out of range detection logic is added to refresh memory blocks for out-of-range addresses, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The column address decoder performs both normal decoding and out-of-range detection functions, eliminating the need for separate detection logic that would consume additional power. This universal approach maintains data integrity while minimizing power consumption by reusing existing circuitry
Solution Approach 2:
The column address decoder automatically detects out-of-range conditions and triggers refresh operations without requiring additional power-consuming detection circuits. The system uses its own existing resources to maintain data integrity
3Reliability
If out of range detection logic is added to refresh memory blocks for out-of-range addresses, then data integrity is maintained, but access time increases
Solution Approach 1:
The column address decoder simultaneously performs decoding and out-of-range detection without requiring separate processing stages. This universal function allows the system to maintain data integrity while avoiding the time penalty of additional detection logic
Solution Approach 2:
The decoder automatically identifies out-of-range addresses and triggers refresh operations in the same processing cycle, eliminating the need for separate detection and response time that would increase overall access time
4Use of energy by moving object
If unnecessary memory capacity is eliminated to improve power conservation and gate efficiency, then power consumption decreases, but the ability to handle out-of-range addresses properly deteriorates
Solution Approach 1:
The patent extracts only the necessary column address decoder functionality required for both normal operation and out-of-range detection. By removing unnecessary memory capacity while retaining the essential decoding logic, the system achieves power conservation while maintaining the ability to properly handle out-of-range addresses
Solution Approach 2:
The column address decoder is designed to universally handle both valid address decoding and out-of-range detection, allowing the system to eliminate unnecessary memory capacity while maintaining proper out-of-range handling capabilities through the multi-functional decoder
Data Source
AI summary
Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.