Column Decoder Segmentation Reduces Power
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Solution Overview
Problem
Conventional column decoders in memory devices experience increased power consumption and reduced decoding speed due to simultaneous transitions in decoded data, leading to potential failure and reliability issues.
Innovation Solution
A column decoder design that decodes a column address into sub-addresses, with specific decoders reversing their outputs based on changes in predetermined bits of the sub-addresses, reducing simultaneous transitions and optimizing control of selection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional column decoder decodes column address into first decoded data to third decoded data, then the column address can be decoded into control signals for selection circuits, but multiple simultaneous transitions occur to the decoded data which increases power consumption and reduces decoding speed
Solution Approach 1:
The column address is segmented into first sub-address and second sub-address, which are decoded separately into first decoded data and second decoded data. This segmentation allows independent decoding of each sub-address, reducing simultaneous transitions in the decoded data and thereby lowering power consumption while maintaining decoding reliability.
Solution Approach 2:
The patent dynamically adjusts the decoding process by conditionally inverting the first decoded data based on the value of a predetermined bit in the second sub-address. This dynamic adjustment optimizes the transition patterns of decoded data, reducing simultaneous transitions and power consumption while ensuring correct decoding operation.
2Productivity
If a conventional column decoder processes successively incremental column address, then all column addresses can be decoded, but multiple simultaneous transitions occur to the decoded data which reduces decoding speed
Solution Approach 1:
By segmenting the column address into multiple sub-addresses that are decoded separately, the patent reduces the number of simultaneous transitions in the decoded data. This segmentation approach accelerates the decoding process by avoiding large-scale simultaneous switching, thereby improving decoding speed while maintaining reliability through separate decoding paths.
Solution Approach 2:
The patent employs dynamic conditional inversion of the first decoded data based on the predetermined bit of the second sub-address. This dynamic adjustment optimizes transition patterns during successive incremental addressing, reducing simultaneous transitions and improving decoding speed while ensuring correct operational reliability.
3Ease of operation
If multiple switches of the first to third selection circuits are simultaneously switched, then the decoded data can respond to column address changes, but power switching loss increases and power consumption is increased
Solution Approach 1:
The selection control is segmented into multiple independent decoded data outputs from separate decoders. This segmentation distributes the switching activity across different decoding paths, reducing simultaneous switch transitions in the selection circuits and thereby minimizing power switching loss while maintaining operational ease.
Solution Approach 2:
The patent dynamically conditions the first decoded data output based on the predetermined bit of the second sub-address. This dynamic control optimizes the switching patterns of the selection circuits, reducing simultaneous switch transitions and power switching loss while ensuring the selection circuits operate correctly and easily.
4Productivity
If the number of times of simultaneous transitions occurring to the decoded data increases, then more column address changes are handled, but power consumption of the column decoder is increased
Solution Approach 1:
The column address processing is segmented into multiple independent sub-address decoding operations. This segmentation reduces the frequency of simultaneous transitions in the decoded data by distributing transitions across separate decoding paths, thereby reducing power consumption while maintaining the ability to handle multiple column address changes.
Solution Approach 2:
The patent employs dynamic conditional inversion of the first decoded data based on the predetermined bit of the second sub-address. This dynamic adjustment optimizes transition patterns during column address processing, reducing the number of simultaneous transitions and associated power consumption while maintaining full column address processing capability.
Data Source
AI summary
A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address.