Coupled Memory Dies for Column and Interconnection Repair
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face limitations in contact density, data rate, and storage density due to interconnection techniques in memory dies, which affect the efficiency and yield of semiconductor systems.
Innovation Solution
Distribute memory access circuitry among multiple semiconductor dies in a stack, incorporating redundancy portions for efficient repair of failures, such as column failures and interconnection issues, by utilizing overprovisioning and intelligent resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional interconnection techniques are used in memory dies, then manufacturing process is simpler, but contact density and data rate are limited
Solution Approach 1:
The patent divides the memory access circuitry into separate components distributed across multiple semiconductor dies. Specifically, it separates memory arrays from memory access circuitry, with each die containing both components. This segmentation allows independent optimization of contact density in memory arrays and data rate in access circuitry, resolving the contradiction between contact density and structural complexity.
Solution Approach 2:
The patent transitions from a planar 2D interconnection structure to a 3D stacked architecture where multiple dies are vertically stacked and interconnected through vertical interconnects. This dimensional change enables higher contact density in the horizontal plane while managing complexity through standardized vertical connection interfaces, thereby improving both contact density and data rate simultaneously.
2Speed
If traditional interconnection techniques are used in memory dies, then device structure is simpler, but data rate is limited
Solution Approach 1:
By segmenting memory access circuitry into separate modules distributed across multiple dies, the patent enables parallel data transmission paths. Each die can independently handle memory access operations, allowing simultaneous data reads/writes across multiple dies, thereby increasing overall data rate without requiring a single complex high-speed interconnection structure.
Solution Approach 2:
The 3D stacked architecture introduces vertical interconnection dimension in addition to horizontal connections. This vertical dimension provides additional data transmission pathways, enabling higher data rates through parallel vertical interconnects while maintaining manageable complexity through standardized stacking interfaces and modular die designs.
3Quantity of substance
If traditional interconnection techniques are used in memory dies, then manufacturing is easier, but storage density is limited
Solution Approach 1:
The patent segments storage functionality across multiple semiconductor dies, with each die containing memory arrays and access circuitry. This distribution allows efficient use of contact density in each individual die while achieving high overall storage density through the stacked configuration. The modular approach simplifies manufacturing of individual dies while enabling high storage density at the system level.
Solution Approach 2:
The 3D stacked architecture exploits the vertical dimension to increase storage density by stacking multiple memory-capable dies. This vertical stacking multiplies the storage capacity without proportionally increasing the footprint area, achieving high storage density while managing interconnection complexity through standardized vertical interfaces and modular die designs.
4Reliability
If redundancy portions are added for repair, then reliability improves, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple independent dies with distributed redundancy portions. Each die contains its own redundancy resources that can independently repair local failures. This segmentation confines complexity to individual die levels rather than requiring system-wide redundancy management, thereby improving reliability while controlling overall device complexity through modular redundancy implementation.
Data Source
AI summary
Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.