Column-by-Column Memory Writing for NVRAM Throughput
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Solution Overview
Problem
Non-volatile random access memory (NVRAM) devices, such as RRAM and STT MRAM, face low write efficiency due to traditional row-by-row writing methods, which can lead to inadequate write throughput when handling large quantities of data.
Innovation Solution
A memory device and method that writes data by column, utilizing a storage unit array with M rows and N columns, where the controller performs a reset operation on storage units in columns and writes values in parallel, improving write efficiency, especially when the number of rows of data exceeds the number of columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional row-by-row writing method is used, then the memory device can write data in a conventional manner, but the write throughput is low and write efficiency is insufficient
Solution Approach 1:
The patent inverts the traditional row-by-row writing approach by implementing column-by-column writing. Instead of selecting one row at a time and writing across columns, the method selects one column at a time and writes down all rows in that column simultaneously. This inversion of the writing direction enables parallel writing operations across multiple storage units, significantly improving write throughput and efficiency.
2Productivity
If row-by-row writing is performed, then the control logic follows conventional design, but the write efficiency deteriorates when handling large quantities of data
Solution Approach 1:
The patent segments the writing process into column-based operations rather than row-based operations. By dividing the storage array into columns and processing one column at a time with simultaneous row-wide writing, the method creates manageable segments that can be processed in parallel. This segmentation approach maintains control logic simplicity while dramatically improving write efficiency for large data quantities.
3Productivity
If parallel writing is implemented across multiple storage units, then write throughput increases, but the requirement for simultaneous voltage application across multiple bit line pairs increases
Solution Approach 1:
The patent merges the writing operations for multiple storage units by applying voltages to all bit line pairs simultaneously during column-based writing. Instead of sequentially writing to each bit line pair, the method combines all writing operations into a single time step by applying appropriate voltages to all relevant bit lines and source lines at the same time. This merging of operations achieves parallel writing across multiple storage units while managing voltage application through coordinated control.
Data Source
AI summary
A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.