Column Multiplexer Bulk Port Voltage Control for Memory Reliability
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Solution Overview
Problem
Miniaturization of semiconductor memory devices leads to increased susceptibility to latch-up phenomena and degradation of PMOS transistors due to the use of write voltages greater than the power supply voltage, which can result in current flow through the bulk of PMOS transistors, causing operational issues and device degradation.
Innovation Solution
Incorporating a control logic circuit to generate a write enable signal that applies a write voltage greater than or equal to the power supply voltage to the bulk port of a column multiplexer circuit, and subsequently applying the power supply voltage to the bulk port after the write operation is completed, thereby preventing latch-up phenomena and reducing transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write voltage greater than power supply voltage is applied to memory cell during write operation, then write operation reliability is improved, but latch-up phenomena occurs in column multiplexer circuit and PMOS transistor degradation occurs
Solution Approach 1:
The bulk port voltage control is segmented into operation-specific zones: during write operations, the bulk port receives write voltage to prevent latch-up; during read/standby operations, it receives power supply voltage for normal transistor operation. This temporal segmentation allows the system to benefit from high write voltage without suffering degradation from continuous exposure.
Solution Approach 2:
The bulk port voltage parameter is dynamically changed based on operation type. The control logic circuit monitors the operation state and adjusts the bulk port voltage accordingly - applying higher write voltage during writes to prevent latch-up, and switching to standard power supply voltage during other operations to prevent transistor degradation.
2Reliability
If write voltage is applied to bulk port during write operation, then latch-up phenomena is prevented, but device complexity increases due to control logic circuit
Solution Approach 1:
The control logic circuit performs multiple functions: it generates write enable signals for the write driver, controls the bulk port voltage switching, and coordinates operation state monitoring. By consolidating these control functions into a single multi-functional block, the patent reduces overall device complexity compared to having separate dedicated circuits for each function.
Solution Approach 2:
The control logic circuit automatically monitors the operation state and autonomously switches the bulk port voltage without requiring external intervention. The circuit self-regulates the voltage application based on internal operation detection, eliminating the need for additional external control mechanisms.
Data Source
AI summary
A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.