Image Sensor Column Output Circuit Noise Reduction
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Solution Overview
Problem
Existing column output circuits in image sensors suffer from reduced signal gain due to parasitic capacitance in global buses, leading to increased noise levels and compromised image quality, and are limited by small buffer amplifier size which affects noise and speed performance.
Innovation Solution
The sample and hold circuits are divided into groups with pairs of buffers connected to global buses, isolating signal and reset voltages, and using differential amplifiers to compute difference signals, reducing noise and increasing efficiency by allowing larger buffer amplifiers and parallel signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If buffer amplifiers are made small to fit the limited space in each column output circuit, then the device complexity is reduced, but the noise performance and speed performance deteriorate
Solution Approach 1:
Multiple column output circuits share a common buffer amplifier through time-division multiplexing. The buffer amplifier is selectively connected to different column lines based on timing signals, allowing one physical buffer to serve multiple columns sequentially. This merging approach eliminates the need for separate buffers in each column circuit, freeing up space while maintaining performance.
Solution Approach 2:
The buffer amplifier is designed to perform multiple functions by serving different column output circuits at different times. Through multiplexing control, a single buffer amplifier handles signal buffering for multiple columns, making it a universal component that replaces multiple dedicated buffers while improving overall system efficiency.
2Device complexity
If buffer amplifiers are made small to fit the limited space in each column output circuit, then the device complexity is reduced, but the speed performance deteriorates
Solution Approach 1:
Multiple column output circuits share a common buffer amplifier through time-division multiplexing. The buffer amplifier is selectively connected to different column lines based on timing signals, allowing one physical buffer to serve multiple columns sequentially. This merging approach eliminates the need for separate buffers in each column circuit, freeing up space while maintaining performance.
Solution Approach 2:
The buffer amplifier connection is dynamically controlled through multiplexing switches that redirect the buffer output to different column lines based on timing signals. This dynamic switching allows the single buffer to service multiple columns in sequence, maintaining fast readout speeds without requiring multiple static buffers.
3Measurement precision
If gain is applied to compensate for reduced signal gain from parasitic capacitance, then the signal recovery is improved, but the noise level increases
Solution Approach 1:
The buffer amplifier extracts and isolates the signal from the parasitic capacitance of the global bus before it reaches the subsequent circuit stages. By placing the buffer between the sample-and-hold capacitor and the global bus, the signal is buffered and isolated, preventing the parasitic capacitance from loading down the signal and reducing gain.
Solution Approach 2:
The buffer amplifier acts as an intermediary component between the sample-and-hold capacitor and the global bus. It provides impedance transformation and signal isolation, protecting the signal from the parasitic capacitance effects of the global bus while maintaining signal integrity and preventing noise amplification.
Data Source
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AI summary
A pixel array in an image sensor includes multiple pixels arranged in rows and columns with each column of pixels electrically connected to a column output line. A sample and hold circuit is electrically connected to each column output line. In one embodiment in accordance with the invention, each sample and hold circuit includes one capacitor for receiving and storing a signal voltage and a second capacitor for receiving and storing a reset voltage. The sample and hold circuits are divided into distinct groups, with each group including two or more sample and hold circuits. A pair of buffers is electrically connected to each distinct group. One global bus receives the signal voltages from at least a portion of buffers and another global bus receives the reset voltages fro at least a portion of the other buffers. The global buses can include one or more signal lines.