Column-Parallel Image Sensor for Low-Latency Inter-Pixel Processing
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Solution Overview
Problem
Conventional image sensors face challenges in achieving high-speed and low-latency inter-pixel image processing due to the large area occupied by image processing circuits, which limits pixel size and number, and requires repetitive signal processing across rows, hindering processing speed.
Innovation Solution
The image sensor incorporates a column-parallel architecture with a pixel array unit, vertical scanning circuit, column-parallel AD conversion unit, column-parallel memory unit, column-parallel inter-pixel image processing unit, and control circuit, allowing for parallel operation of AD conversion and inter-pixel image processing, reducing latency and increasing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one image processing circuit is disposed for one pixel to perform parallel image processing, then image processing speed is improved and latency is reduced, but the area occupied by image processing circuits increases, making it difficult to make pixel portion large and increase the number of pixels
Solution Approach 1:
The patent segments the image processing function from individual pixels and concentrates it in a dedicated image processing circuit that operates on column-parallel data. Instead of having processing circuits at each pixel, the system divides the sensor into columns and processes each column's data separately in a shared processing unit, reducing per-pixel area while maintaining processing capability.
Solution Approach 2:
The patent merges multiple pixel data streams from the same column into a single processing path. By combining data from multiple pixels before processing and performing operations on the combined data, the system achieves inter-pixel image processing without requiring separate processing circuits for each pixel, thus reducing overall circuit area.
2Device complexity
If signal processing is performed by directly selecting pixel outputs by a multiplexer in conventional configuration, then circuit implementation is simplified, but image processing takes time due to repetitive processing of one row after scanning and selecting pixel outputs
Solution Approach 1:
The patent performs preliminary organization of pixel data by column before processing. Instead of scanning and selecting pixel outputs row by row, the system pre-arranges data in column-parallel buffers, allowing the image processing circuit to directly access and process relevant pixel data without sequential scanning, thus reducing processing time while maintaining circuit simplicity.
3Productivity
If image processing is performed with high speed and low latency, then processing efficiency is improved, but the area of one unit pixel including image processing circuit becomes large, making it difficult to increase the number of pixels
Solution Approach 1:
The patent creates a universal image processing circuit that can handle data from multiple pixels and columns. This single processing unit performs inter-pixel operations on column-parallel data, serving the function of multiple individual processing circuits would otherwise be needed. The circuit's ability to process data from any column makes it multi-functional, reducing the total number of processing elements required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed and low-latency inter-pixel image processing, allowing the image sensor to operate with substantially the same processing speed as AD conversion, while maintaining flexibility in memory size and connection configurations, and reducing circuit size.
Implementation Method 1
a plurality of pixels two-dimensionally arranged in a matrix and having a photoelectric conversion function
Data Source
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AI summary
[Object] To perform inter-pixel image processing with lower latency and higher speed. [Solution] An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.