Column Parallel Imager Architecture with Dual-Side ADC Placement
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Solution Overview
Problem
Existing solid-state imagers with column-parallel architectures face challenges in efficiently processing and digitizing analog signals due to the complexity and space requirements of analog-to-digital converters, which become more complicated as pixel density increases, leading to inefficient use of design space and manufacturing errors.
Innovation Solution
The solution involves arranging processing elements, including sample and hold circuits, differential amplifiers, and analog-to-digital converters, in multiple slices above and below the pixel array, allowing for simultaneous readout and digitization of multiple columns, and optionally sharing analog-to-digital converters among processing elements to reduce the width required for each pixel column and improve component density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If analog-to-digital converters are made narrower to scale with shrinking pixel sizes, then pixel density can be increased, but the aspect ratio of converters increases making layout more difficult
Solution Approach 1:
The patent transitions from a single-sided converter arrangement to a dual-sided arrangement where converters are positioned above and below the pixel array. This dimensional change allows converters to be distributed across multiple layers, reducing the aspect ratio constraint and enabling narrower converters while maintaining manufacturable layouts.
Solution Approach 2:
The patent divides the converter array into multiple segments positioned at different locations (above and below the pixel array). This segmentation allows each converter to be independently positioned and sized, reducing the overall width requirement and enabling higher pixel density without proportionally increasing layout difficulty.
2Productivity
If multiple analog-to-digital converters are provided for each column, then readout speed increases, but device complexity and space requirements increase
Solution Approach 1:
The patent merges multiple converter functions into shared converter units that can serve multiple columns. By positioning converters above and below the pixel array, the system can time-multiplex or space-multiplex converter resources, achieving high readout speed without requiring a dedicated converter for every single column.
Solution Approach 2:
The patent designs converters with multi-functionality to serve multiple columns through shared resources. The converters positioned above and below the pixel array can be configured to handle multiple column readout operations, reducing the total number of converters needed while maintaining high readout throughput.
3Measurement precision
If pixel size continues to shrink, then image resolution improves, but the minimum spacing required between converters becomes significant relative to pixel column width
Solution Approach 1:
The patent resolves the spacing issue by moving converters to a second dimension (above and below the pixel array) rather than constraining them within the same plane. This allows converters to be positioned at optimal distances from pixel columns without being limited by lateral spacing constraints, enabling smaller pixel sizes while maintaining manageable converter spacing.
Data Source
AI summary
An imaging apparatus and a method using column processing circuits arranged in multiple rows for processing pixels in a pixel array.