Column Plane Error Encoding for Faster Memory Test Diagnosis
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Solution Overview
Problem
High-density semiconductor memory devices require extensive time and resources for read operations during test procedures, consuming significant equipment resources to transmit and process large volumes of data, which hampers efficient error detection and diagnosis.
Innovation Solution
Incorporation of column plane compression circuitry that compresses output data and encodes error codes to identify error locations, patterns, and failure modes within the memory cell array, allowing for more precise error detection and diagnosis without the need for multiple individual column plane read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data is read out from high density memory during test operations, then complete error detection is achieved, but considerable time and equipment resources are consumed
Solution Approach 1:
The patent extracts only the essential error detection information from the complete memory data by implementing column plane compression circuitry that generates condensed error codes representing multiple column planes. This extraction principle allows complete error detection coverage while significantly reducing the volume of data that must be transmitted and processed during test operations.
Solution Approach 2:
The patent segments the memory test data into column plane groups and processes each segment independently through compression circuitry. By dividing the large volume of memory data into manageable column plane segments and generating separate error codes for each segment, the system achieves comprehensive error detection while reducing overall transmission and processing time.
2Reliability
If all data is read out from high density memory during test operations, then complete error detection is achieved, but significant equipment resources are consumed for data transmission and processing
Solution Approach 1:
The patent extracts only the essential error detection information from the complete memory data by implementing column plane compression circuitry that generates condensed error codes representing multiple column planes. This extraction principle allows complete error detection coverage while significantly reducing the volume of data that must be transmitted and processed during test operations.
Solution Approach 2:
Instead of reading out all memory data and then processing it to detect errors, the patent inverts the approach by using compression circuitry to generate error codes directly from the memory data during the read operation. This inversion allows error detection to occur concurrently with data retrieval, eliminating the need for separate processing steps and improving equipment resource efficiency.
3Loss of time
If traditional single-bit pass/fail flag methods are used, then test operation time is reduced, but detailed error information and diagnosis capability are lost
Solution Approach 1:
The patent changes the parameter of error representation from a single binary pass/fail flag to multi-bit error codes that encode detailed information about error locations, patterns, and affected column planes. This parameter change maintains rapid test operation while preserving comprehensive error diagnostic information, as the compression circuitry generates error codes that can be decoded to identify specific failed column planes and error patterns.
Solution Approach 2:
The patent introduces column plane error codes as an intermediary representation between the raw memory data and the final pass/fail determination. These error codes serve as a compact intermediary that preserves detailed error information while requiring minimal transmission and processing resources, bridging the gap between fast single-bit flags and comprehensive full-data analysis.
Data Source
AI summary
An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.