Column-Read Memory with Programmable Die Offsets for Parallel Data Access
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Solution Overview
Problem
Large-scale similarity searches in machine learning and artificial intelligence applications face challenges due to the compute and memory intensity of high-volume data, with hashing methods providing imperfect conversions and degrading search accuracy, and current stochastic associative memories struggling to meet throughput demands.
Innovation Solution
The implementation of a compute device with column-read enabled memory using a three-dimensional cross-point architecture, which enables efficient column read operations by determining programmable or dynamic die offsets and per-die addressing, reducing the number of read operations and improving read performance by accessing multiple tiles in parallel and performing matrix calculations within memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hashing methods are used to perform stochastic associative searches, then search speed is improved, but search accuracy deteriorates due to imperfect conversion of data from one space to another
Solution Approach 1:
The patent introduces column-read enabled memory as an intermediary between the query data and the database entries. This memory architecture with three-dimensional cross-point structure and programmable die offsets acts as a mediator that enables efficient columnar access patterns, allowing direct comparison of query vectors with database vectors in the original space without hashing conversion, thus maintaining both speed and accuracy
2Productivity
If the database is partitioned into clusters to improve effective search speed, then throughput is improved, but device complexity increases due to cluster management and representative selection
Solution Approach 1:
The patent applies segmentation by dividing the database into multiple partitions stored in different banks of the column-read enabled memory. Each partition can be accessed independently through bank-specific addressing, allowing parallel search operations across partitions. This segmentation improves throughput by enabling simultaneous processing while the standardized addressing scheme keeps management complexity manageable
Solution Approach 2:
The patent transitions from traditional row-based or flat database organization to a three-dimensional memory architecture with row, column, and bank dimensions. This dimensional reorganization allows efficient cluster-based search by enabling independent access to different partitions (banks) and columns simultaneously, improving throughput while the structured addressing keeps complexity controlled
3Speed
If column-read enabled memory with three-dimensional cross-point architecture is used, then read performance is improved through parallel operations, but device complexity increases due to programmable die offsets and per-die addressing
Solution Approach 1:
The patent implements dynamic die offset programming that allows the memory system to adaptively adjust addressing parameters based on the specific search operation being performed. The programmable die offsets can be dynamically configured for different column read operations, enabling flexible parallel access patterns while the control logic manages the complexity of dynamic reconfiguration
Solution Approach 2:
The column-read enabled memory architecture provides universal access capabilities that can handle various search patterns (cluster-based, column-based, partition-based) through a unified addressing scheme. The per-die addressing mechanism serves multiple functions including partition identification, column selection, and offset adjustment, reducing the need for separate complex control mechanisms for each access pattern
Data Source
AI summary
Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.