Column Redundancy Data Architecture for Memory Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory chips face defects during manufacturing or operation, leading to reduced production yield and operational speed limitations due to combinational delay in column redundancy logic, which existing redundancy schemes struggle to address effectively.
Innovation Solution
A column redundancy data architecture that uses a division-based approach, where each division includes a set of columns, allowing for efficient detection and skipping of defective columns through dynamic address calculations and match bits, enabling faster identification and compensation of defects without compromising read/write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional column redundancy schemes are used to address memory defects, then defect coverage is improved, but combinational delay increases and read/write speed decreases
Solution Approach 1:
The memory array is divided into multiple divisions, and the column redundancy data array is segmented to store information for different divisions separately. This segmentation allows the defect detection and skipping logic to operate on smaller, independent segments, reducing the overall combinational delay while maintaining comprehensive defect coverage across the entire memory array.
2Reliability
If comprehensive redundancy schemes are implemented to address all defects, then reliability is improved, but production yield decreases due to stricter chip rejection criteria
Solution Approach 1:
The patent implements a selective redundancy approach where only the necessary portion of redundancy logic is activated based on the actual defect distribution in the memory array. By using match bits to identify only the defective columns within each division and skipping only those specific columns, the system provides adequate defect assurance without requiring comprehensive redundancy that would lead to excessive chip rejection and reduced production yield.
3Measurement precision
If detailed column defect tracking is implemented, then defect detection precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential defect information needed for column skipping by using match bits that indicate whether columns in each division are defective. Instead of tracking detailed defect information for every column, the system extracts and stores only the critical match bit data in the column redundancy data array, significantly reducing device complexity while maintaining sufficient defect detection precision for effective column skipping.
Data Source
AI summary
Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.