Column Redundancy Circuit for Memory Yield
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Solution Overview
Problem
The increasing number of defective memory cells in memory devices due to miniaturization advancements leads to decreased yield, as spare memory cells also become defective, reducing the overall yield of memory devices.
Innovation Solution
A memory device with column redundancy is implemented, featuring a column decoder with repair circuits that select alternative bit lines when a repair column address matches a received column address, allowing substitution of defective memory cells with spare cells, thereby correcting errors and increasing device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If miniaturization process technology is advanced to increase memory capacity, then memory capacity is improved, but the number of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple repair circuits (first repair circuit, second repair circuit, third repair circuit) with repair column addresses before defects occur. When a defect is detected in a memory cell, the corresponding repair circuit is activated to redirect the column address to a spare bit line, avoiding the defective cell. This proactive setup enables immediate defect compensation without requiring system reconfiguration.
Solution Approach 2:
The patent uses intermediary elements (repair circuits and spare bit lines) to mediate between defective memory cells and functional memory cells. When a column address points to a defective cell, the repair circuit acts as an intermediary to translate this address to a corresponding spare bit line, thereby routing signals around the defect. This intermediary mechanism allows the system to maintain normal operation despite the presence of defective cells.
2Productivity
If spare memory cells are incorporated to increase yield, then yield is improved, but the yield of spare memory cells also decreases due to defects
Solution Approach 1:
The patent segments the redundancy management into multiple independent repair circuits (first repair circuit for first spare bit line, second repair circuit for second spare bit line, third repair circuit for third spare bit line). Each repair circuit independently manages a specific spare bit line and its corresponding defective bit line. This segmentation ensures that a defect in one spare memory cell does not compromise the functionality of other spare cells, as each has its dedicated repair circuit.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing multiple repair column addresses in different repair circuits. When a defect is detected, the system changes the column address routing parameter from the original defective bit line to a spare bit line through the appropriate repair circuit. This parameter change allows dynamic adaptation to defects while maintaining system functionality.
3Reliability
If repair circuits are added to handle defective cells, then defective cell compensation is improved, but device complexity increases
Solution Approach 1:
The patent merges the repair functionality into the existing column decoder structure. The repair circuits are integrated with the column address decoding logic, allowing defect compensation to occur within the same operational framework as normal memory access. This merging approach avoids creating a separate complex repair subsystem while still providing comprehensive defect coverage through multiple repair circuits.
Data Source
AI summary
A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.