Column Redundancy Circuit with Pre-Decoding for Faster Column Shift
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Solution Overview
Problem
Column redundancy circuits in memory devices occupy a large area and require significant setup time to replace defective columns, hindering efficient operation.
Innovation Solution
A column redundancy circuit with a pre-decoder unit, main decoder unit, shift logic unit, and multiplexer unit that performs OneHot and Binary to Thermometer Code decoding operations to minimize area and reduce setup time for column redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a column redundancy circuit is implemented to replace defective columns, then reliability is improved, but area occupied increases and setup time increases
Solution Approach 1:
The column address is divided into upper and lower parts, with separate pre-decoders handling each part. This segmentation allows the redundancy circuit to process address bits in parallel stages, reducing the overall circuit area while maintaining full redundancy coverage capability
Solution Approach 2:
Pre-decoder units perform preliminary decoding of upper and lower column address parts before the main decoding stage. This preliminary action prepares the address signals in advance, enabling faster main decoder operation and reducing the setup time required for column redundancy operations
2Reliability
If a column redundancy circuit is implemented to replace defective columns, then reliability is improved, but setup time increases
Solution Approach 1:
The decoding process is segmented into multiple stages: pre-decoding of upper column address parts, pre-decoding of lower column address parts, and main decoding. This multi-stage segmentation allows parallel processing of address bits, significantly reducing the total setup time compared to sequential full-address decoding
Solution Approach 2:
The pre-decoder units perform preliminary decoding operations on upper and lower column address parts before the main decoder processes the complete address. This preliminary action prepares decoded signals in advance, reducing the critical path delay and minimizing setup time for column redundancy operations
3Reliability
If traditional column redundancy circuit design is used, then reliability is improved, but device complexity increases
Solution Approach 1:
The column redundancy circuit is divided into modular pre-decoder units and main decoder units. Each pre-decoder handles specific address bits independently, and the main decoder integrates these partial results. This modular segmentation reduces overall circuit complexity by breaking down the large decoding function into smaller, manageable units that can be designed and verified independently
Data Source
AI summary
An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.