Column Select Signal Circuit for DRAM 2-Bit Error Correction
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) faces challenges in correcting 2 bits errors due to simultaneous defects in adjacent storage units, as existing Error Correcting Codes (ECC) can only correct 1 bit errors.
Innovation Solution
The implementation of a column select signal cell circuit and a bit line sense circuit design, where two adjacent bit lines are connected to different sense amplifier groups, allowing for the detection and correction of 2 bits errors without altering the existing error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adjacent storage units share the same sense amplifier group, then device complexity is reduced, but 2 bits errors cannot be detected and corrected
Solution Approach 1:
The patent segments the storage array into multiple storage unit groups, where each group is associated with a dedicated sense amplifier group. Adjacent storage units are distributed across different groups, ensuring that 2 bits errors affecting adjacent units can be detected and corrected by the ECC circuit, as each group's errors are independently processed.
Solution Approach 2:
The patent introduces a new dimension of organization by grouping storage units into multiple storage unit groups with different sense amplifier group assignments. This dimensional reorganization allows the system to distinguish between errors in different groups, enabling the ECC to detect and correct 2 bits errors that would otherwise be indistinguishable within a single sense amplifier group.
2Ease of manufacture
If all bit lines are connected to the same sense amplifier group, then manufacturing process is simplified, but adjacent 2 bits errors exceed ECC correction capability
Solution Approach 1:
The patent divides the bit lines into multiple sets, with each set connected to a different sense amplifier group. This segmentation ensures that adjacent bit lines are distributed across different groups, allowing the ECC circuit to identify and correct 2 bits errors by comparing error patterns across groups, while maintaining relatively simple manufacturing processes.
Solution Approach 2:
The patent adds a grouping dimension to the bit line organization, creating multiple storage unit groups that are differently assigned to sense amplifier groups. This dimensional approach enables the system to track and correct 2 bits errors without significantly complicating the manufacturing process, as the grouping can be implemented through standard memory array design practices.
3Reliability
If storage units are grouped into multiple storage unit groups with different sense amplifier groups, then 2 bits errors can be corrected, but device complexity increases
Solution Approach 1:
The patent segments the storage array into multiple storage unit groups, each associated with different sense amplifier groups. This segmentation enables the ECC circuit to detect and correct 2 bits errors by analyzing error patterns across groups, while the segmentation itself is implemented through straightforward memory organization techniques that minimize additional complexity.
Solution Approach 2:
The patent designs the storage unit grouping system to serve multiple functions: it enables 2 bits error correction, maintains compatibility with existing ECC circuits, and preserves standard memory operation modes. The grouping structure is universally applicable to different memory configurations and can be integrated with existing memory architectures without requiring fundamental redesigns.
4Reliability
If bit lines are distributed to different sense amplifier groups, then data integrity is improved, but wiring complexity increases
Solution Approach 1:
The patent segments bit lines into multiple sets that are distributed to different sense amplifier groups. This segmentation improves data integrity by enabling 2 bits error detection and correction, while the wiring configuration follows regular patterns that can be implemented using standard memory layout techniques, thereby limiting the increase in wiring complexity.
Solution Approach 2:
The patent applies local quality by assigning specific bit line sets to specific sense amplifier groups in a systematic manner. This localized assignment optimizes the wiring configuration for each region of the memory array, ensuring that adjacent bit lines are appropriately distributed to different groups for error detection while maintaining efficient local connections that minimize overall wiring complexity.
Data Source
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AI summary
A column select signal cell circuit, a bit line sense circuit and a memory are disclosed in the present application. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group, and the first storage unit group and the second storage unit group are adjacently arranged. According to the technical solution, two adjacent bit lines are connected to different sense amplifier groups, and when read errors occur simultaneously on the two adjacent bit lines, error data may be detected and corrected by an Error Correcting Code (ECC).