Column-Shared ADC Architecture for High-Frame-Rate Image Sensors
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Solution Overview
Problem
Existing image sensor technologies face challenges in minimizing sensor size, power consumption, and area occupancy while maintaining high frame rates and image quality, particularly in endoscopy applications where small pixel sizes and parallel readout channels are required, leading to inefficiencies in analog-to-digital conversion and correlated double sampling processes.
Innovation Solution
The proposed analogue-to-digital converter architecture employs a single operational amplifier and read-out capacitors per column, allowing parallel readout of reset values and sequential conversion of signal values, enabling correlated double sampling in the analogue domain with a single digital output register, which reduces the number of conversions and optimizes area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADC converters are used (one per column), then the conversion speed and frame rate are improved, but the area occupancy and device complexity increase
Solution Approach 1:
The pixel array is divided into multiple columns, each with its own dedicated read-out capacitor. This segmentation allows parallel processing of reset values across columns while using a single shared ADC converter, resolving the contradiction between conversion speed and area occupancy.
Solution Approach 2:
Multiple column outputs are merged into a single read-out path that shares one ADC converter. The read-out capacitors from multiple columns are combined through switching circuitry to sequentially feed the single converter, reducing area while maintaining throughput through time-multiplexed operation.
2Productivity
If multiple ADC converters are used (one per column), then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
A single ADC converter is designed to perform multiple functions by sequentially serving different columns. The converter acts as a universal resource that processes signals from multiple sources through time-multiplexed operation, reducing total power consumption while maintaining conversion speed through parallel capacitor charging.
Solution Approach 2:
Reset values are pre-charged into read-out capacitors for multiple columns before conversion begins. This preliminary action allows the ADC to process columns sequentially without waiting for charge accumulation, maintaining conversion speed while using a single lower-power converter.
3Area of stationary object
If sequential conversion is used, then the area occupancy is reduced, but the operation time increases
Solution Approach 1:
While one column is being converted, read-out capacitors for other columns are continuously charging their reset values in parallel. This continuous useful action ensures that the sequential conversion process does not have idle waiting time, maintaining high operation speed with minimal area occupancy.
Solution Approach 2:
Reset values are preliminarily charged into read-out capacitors before the conversion phase begins. This preliminary charging action allows the ADC to immediately start conversion without delay, reducing operation time despite sequential processing.
4Area of stationary object
If a single ADC converter is used, then the area occupancy and power consumption are reduced, but the conversion precision may be compromised
Solution Approach 1:
The conversion process is segmented into two distinct phases: reset value sampling and signal value conversion. This segmentation allows the single ADC to accurately measure each phase separately, maintaining conversion precision by dedicating specific time windows to each measurement without interference.
Solution Approach 2:
The ADC operates in periodic cycles, alternating between sampling reset values and converting signal values. This periodic action with well-defined timing ensures that each conversion phase completes with sufficient precision before the next phase begins, maintaining measurement accuracy despite sequential operation.
Data Source
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AI summary
An analogue to digital converter is provided for digital imaging devices, in which a pixel column is sampled by a respective capacitor. In a reset phase of operation, each pixel in the row under consideration is reset, and an operational amplifier operating in a voltage follower mode is coupled to all the sampling capacitors in parallel to obtain the reset values of the pixels sensors of that row, and the in an imaging phase of operation, the inverting input of the operational amplifier operating in a comparator mode is coupled to each capacitor in turn after activating the respective pixel sensor, while exposing the non inverting signal to an analog ramp reference voltage so that the timing of the toggling of the operational amplifier reflects the value of the pixel under consideration, corrected for the reset value.