Column-Wise Neural Processing Core for Lower Peak Power
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Solution Overview
Problem
Conventional synaptic memory arrays in neural processing cores face issues of high peak power consumption and large footprint due to simultaneous current draining and the need for extensive peripheral sensing circuits, which are not optimal for edge intelligence applications requiring compact and energy-efficient solutions.
Innovation Solution
A neural processing core that controls synaptic memory cells in a column-wise manner, utilizing a synaptic memory array with minimized footprint and shared peripheral sensing circuits, enabling time-multiplexing for efficient power and energy usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous current draining is used in conventional synaptic memory arrays, then computing throughput is improved, but peak power consumption increases
Solution Approach 1:
The patent implements sequential column-wise processing where memory cell columns are activated one at a time in a periodic manner rather than simultaneously. Each column is selected by activating its corresponding column select line in sequence, transforming the continuous simultaneous operation into discrete periodic cycles. This reduces peak power consumption while maintaining computational throughput through time-multiplexed operation.
Solution Approach 2:
The patent divides the synaptic memory array into multiple independently controllable columns, each with its own column select line. By segmenting the array into column units that can be processed separately and sequentially, the system avoids the need to activate all columns simultaneously, thereby reducing peak power consumption while still achieving high throughput through rapid sequential processing.
2Measurement precision
If extensive peripheral sensing circuits are used in conventional synaptic memory arrays, then measurement precision is improved, but device footprint increases
Solution Approach 1:
The patent implements shared peripheral sensing circuits that serve multiple memory cell columns through time-multiplexed operation. A single sensing circuit is sequentially connected to different columns via column select lines, allowing one sensing unit to perform the measurement function for multiple columns. This universal approach maintains measurement precision while dramatically reducing the total chip area required for sensing infrastructure.
Solution Approach 2:
The patent merges the sensing functions for multiple columns into a single shared sensing circuit rather than providing dedicated sensing circuits for each column. By combining these functions and using temporal multiplexing to share the sensing resource across different columns, the system achieves the required measurement precision with minimal chip area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact, power-efficient, and energy-efficient neural processing core with reduced chip area and lower power consumption, suitable for edge intelligence applications.
Implementation Method 1
since the memristor's conductance behaves like a synaptic weight, then according to Kirchhoff's law, the combined bit-line current of each column that flows through the Source Line (SLi) would correspond to the weighted sum of the corresponding neuron
Implementation Method 2
the source line current of a 2T2R cell is equal to a differential of the positive current (Ii,j_p) and the negative current (Ii,j_n), which is further proportional to xi×(Gpos−Gneg), i.e., the product of xi and the differential of conductance between positive weight memristor (Gpos) and negative weight memristor (Gneg)
Data Source
AI summary
A neural processing core for a neural network is provided, which includes: a synaptic memory array including synaptic memory cells arranged in a plurality of memory cell rows and columns; a plurality of first input activation lines connected to the plurality of memory cell rows, respectively, of the synaptic memory array and configured to receive a plurality of first input activation signals, respectively, to the plurality of memory cell rows; and a plurality of first sensing lines connected to the plurality of memory cell columns, respectively, of the synaptic memory array and configured to output a plurality of first analog electrical signals, respectively, from the plurality of memory cell columns. In particular, the neural processing core is configured to control the synaptic memory cells of the synaptic memory array in a column-wise manner. There is also provided a corresponding method of operating the neural processing core for a neural network.