Columnar Capacitor Stacked Structure for High Density Memory
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Solution Overview
Problem
The miniaturization of semiconductor process nodes poses challenges in forming capacitor structures with small capacitor holes, leading to low capacitance in columnar capacitors, as existing technologies struggle to effectively create and support the necessary electrode and dielectric layers.
Innovation Solution
A method involving the formation of a stacked structure with a bottom dielectric layer, sacrificial layer, and top dielectric layer, where capacitor holes are formed, and subsequent layers are built to increase capacitance by using the top dielectric layer as a supporting layer after its removal, allowing the formation of additional dielectric and electrode layers that enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the capacitor hole size is reduced to accommodate smaller process nodes, then the device density is improved, but the capacitance decreases
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional stacked capacitor structure. Multiple capacitor structures are stacked vertically on the same substrate area, effectively utilizing the vertical dimension to increase total capacitance while maintaining small capacitor hole areas for high device density.
Solution Approach 2:
The capacitor structure is segmented into multiple independent capacitor units stacked vertically. Each capacitor unit consists of its own electrode layers and dielectric layers, allowing the total capacitance to be the sum of individual capacitor capacitances while each capacitor hole remains small.
2Quantity of substance
If additional dielectric and electrode layers are formed to increase capacitance, then the capacitance is improved, but the process complexity increases
Solution Approach 1:
A sacrificial layer is formed in advance at the desired location where the capacitor structure will be built. This sacrificial layer serves as a template and support structure during the formation of multiple dielectric and electrode layers, simplifying the overall process by providing a pre-established framework.
Solution Approach 2:
The sacrificial layer acts as an intermediary structure that facilitates the formation of the stacked capacitor. It provides mechanical support during the multi-layer formation process and is later removed to create the final capacitor structure, simplifying the manufacturing process by serving as a temporary aid.
Data Source
AI summary
A method of producing a semiconductor memory device includes following operations. A substrate is provided. A stacked structure is formed on the substrate. Capacitor holes arranged at intervals are formed in the stacked structure. Bottom electrode layers are formed in the capacitor holes. A top-layer dielectric layer is removed. A first capacitor dielectric layer is formed on exposed surfaces of a sacrificial layer and surfaces of upper parts of the bottom electrode layers. A first top electrode layer is formed on a surface of the first capacitor dielectric layer. Multiple openings are formed in the first top electrode layer and first capacitor dielectric layer. The sacrificial layer is removed through the openings. A second capacitor dielectric layer is formed. A second top electrode layer is formed on a surface of the second capacitor dielectric layer.