Columnar Conductor Substrate for Stacked Semiconductor Packages
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in achieving high performance and compact size due to the need for complex wire bonding and through-silicon via (TSV) processes, which increase manufacturing costs and complexity.
Innovation Solution
A semiconductor package design that includes a substrate with columnar conductors extending from the substrate to connect stacked semiconductor chips, eliminating the need for wire bonding and simplifying the manufacturing process by directly connecting chips to the substrate, thereby reducing signal paths and stress concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding or through-silicon via (TSV) processes are used to connect stacked semiconductor chips, then electrical connection between chips and substrate is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the complex wire bonding and TSV processes from the semiconductor packaging system. Instead, it uses a simplified columnar conductor structure that directly connects the substrate to the semiconductor chip, removing unnecessary intermediate steps while maintaining electrical connection functionality
Solution Approach 2:
The patent inverts the traditional connection approach by placing columnar conductors on the substrate rather than creating complex vias through the chip. This inversion simplifies the manufacturing process by forming conductors on the substrate surface and extending them upward, eliminating the need for chip perforation and complex via filling processes
2Reliability
If wire bonding or TSV processes are used to connect stacked semiconductor chips, then electrical connection between chips and substrate is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes expensive wire bonding and TSV processes from the manufacturing system, replacing them with a cost-effective columnar conductor approach that uses simpler materials and processes while achieving the same electrical connection function
Solution Approach 2:
The patent employs inexpensive columnar conductors made from simple materials that can be easily formed and removed if needed, replacing expensive and complex wire bonding materials and TSV filling materials while maintaining reliable electrical connection
3Reliability
If stacked semiconductor chips are connected using traditional methods, then electrical connection is established, but signal transfer speed and power consumption are compromised
Solution Approach 1:
The patent transitions from planar wire bonding connections to three-dimensional columnar conductor connections that extend vertically from the substrate. This dimensional change creates shorter and more direct signal paths, improving signal transfer speed while reducing electromagnetic interference
Solution Approach 2:
The patent inverts the connection geometry by having columnar conductors rise from the substrate rather than wires looping from the chip. This inversion creates more direct signal paths with fewer bends and transitions, enhancing signal integrity and transfer speed
4Reliability
If wire bonding or TSV processes are used, then electrical connection is achieved, but manufacturing process time increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming columnar conductors on the substrate before chip mounting. This allows subsequent chip attachment and wire bonding to proceed more quickly without waiting for complex via formation and filling processes, reducing overall manufacturing cycle time
Solution Approach 2:
The patent extracts and eliminates time-consuming TSV drilling, etching, and filling processes from the manufacturing sequence, replacing them with a simplified columnar conductor formation process that can be completed in fewer steps and with shorter cycle times
Data Source
AI summary
A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.