Columnar Grain Embedded Capacitors in 3D Bonded Semiconductors

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Solution Overview

Problem

Three-dimensional (3D) semiconductor structures with embedded capacitors exhibit high resistivity, leading to a decreased quality factor (Q), which affects their energy efficiency and performance.

Innovation Solution

A 3D bonded semiconductor structure is developed with metallic capacitor plate structures having a columnar grain microstructure and a high-k dielectric material between them, along with dummy metallic pad structures, to enhance the quality factor by reducing resistivity and improving mechanical integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional oxide-oxide bonding with through-silicon-vias is used to connect wafers, then mechanical integrity is achieved, but electrical resistance increases and quality factor decreases

Engineering Contradiction:
Improvemechanical integrityVSAvoidelectrical resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent combines oxide-oxide bonding and metal-to-metal bonding into a single simultaneous bonding process. The metallic capacitor plate structures are embedded in the bonding oxide layers, allowing both mechanical bonding strength and low-resistance electrical contact to be achieved together through one bonding operation rather than separate steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding structure uses composite materials consisting of both oxide layers (for mechanical bonding strength) and metallic capacitor plate structures (for low electrical resistance). This composite approach allows the structure to simultaneously achieve mechanical integrity and low electrical resistance, resolving the contradiction between these two requirements.

Inventive Principle:
Principle #40Composite materials

2Adaptability or versatility

If embedded capacitors are added to 3D semiconductor structures, then functionality is improved, but electrical resistivity increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidelectrical resistivity
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent changes the microstructural parameters of the metallic capacitor plate structures by controlling grain size and orientation. By creating fine-grained or columnar grain structures through specific processing conditions, the electrical resistivity is reduced while maintaining the capacitive functionality, thus resolving the contradiction between adding functionality and increasing resistivity.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If metallic capacitor plate structures with fine grain structure are formed, then electrical resistivity decreases, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical resistivityVSAvoidmanufacturing complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the metallic capacitor plate structures with controlled grain structures before the bonding process. The metallic layers are deposited and processed to achieve fine-grained or columnar grain structures in advance, so that when bonding occurs, the low-resistance properties are already established without requiring additional complex processing steps after bonding.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure achieves a lower electrical resistivity and an improved quality factor (Q) for the embedded capacitors, enhancing the energy efficiency and performance of the 3D semiconductor structure.

Implementation Method 1

The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q

Methodology Applied
Scientific EffectGrain boundary scattering:

Implementation Method 2

oxide-oxide bonding is performed to physically connect two wafers

Methodology Applied
Scientific EffectOxide bonding:

Implementation Method 3

A high-k dielectric material is present between the first and second metallic capacitor plate structures

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS10141392B2Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor
Publication Date: 2018.11.27 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10141392B2 patent drawing
  • US10141392B2 patent drawing
  • US10141392B2 patent drawing

AI summary

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic capacitor plate structure embedded therein, wherein each metallic capacitor plate structure has a columnar grain microstructure. A high-k dielectric material is present between the first and second metallic capacitor plate structures. The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q.