Non-volatile Semiconductor Storage Device with Columnar Memory Strings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional semiconductor storage devices face challenges in increasing memory cell integration due to reduced reading current as the number of memory cells in each memory string increases, making read operations more difficult and potentially limiting device performance.
Innovation Solution
A non-volatile semiconductor storage device with a memory cell array featuring memory strings comprising four or more columnar body semiconductor layers, an electric charge storage layer, and multiple conductive layers functioning as control electrodes for memory transistors and back-gate transistors, allowing for improved control and increased memory cell integration while maintaining effective read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in each memory string is increased to improve integration density, then the integration density is improved, but the reading current is reduced making read operations more difficult
Solution Approach 1:
The memory string is segmented into multiple columnar body semiconductor layers (first, second, third, and fourth columnar portions) that are connected through joining portions. This segmentation allows the current path to be distributed across multiple parallel paths, maintaining sufficient reading current even as the total number of memory cells increases for higher integration density.
Solution Approach 2:
The patent transitions from a conventional two-dimensional memory arrangement to a three-dimensional structure with columnar body semiconductor layers extending vertically. Multiple columnar portions are arranged in the vertical dimension and connected through joining portions, enabling increased integration density while maintaining effective read operations through the three-dimensional current distribution.
2Quantity of substance
If the number of memory cells in each memory string is increased to improve integration density, then the integration density is improved, but the resistance in the current path increases
Solution Approach 1:
The current path is segmented into multiple parallel paths through the first, second, third, and fourth columnar portions connected via joining portions. This segmentation reduces the effective resistance in each individual path while maintaining high integration density through the multi-columnar structure.
Solution Approach 2:
Multiple columnar body semiconductor layers are merged through joining portions to form an integrated three-dimensional structure. This merging creates parallel current paths that reduce overall resistance while achieving high integration density in the vertical dimension.
Data Source
AI summary
A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portions, and a joining portion formed to join the lower ends thereof. An electric charge storage layer is formed to surround a side surface of the columnar portions. A first conductive layer is formed to surround a side surface of the columnar portions as well as the electric charge storage layer. A plurality of second conductive layers are formed on side surfaces of the joining portion via an insulation film, and function as control electrodes of a plurality of back-gate transistors formed at a respective one of the joining portions.