Columnar Non-Volatile Memory With Opposite-Side Gate Electrodes
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Solution Overview
Problem
The scaling down of non-volatile semiconductor devices poses challenges in achieving operational reliability due to increased integration demands in semiconductor products, which require smaller form factors with high data processing capabilities.
Innovation Solution
A non-volatile memory device design featuring semiconductor columns with gate and control gate electrodes on opposite sides, a charge storage layer between them, and insulation layers to control channel regions, allowing for efficient data storage and retrieval with reduced voltage stress on the charge storage layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If non-volatile semiconductor devices are scaled down to achieve smaller form factors, then integration density increases, but operational reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertical structures with semiconductor columns extending in the vertical direction. Multiple gate electrodes are positioned at different heights along the column, enabling control of channel regions at different vertical levels. This dimensional change allows increased storage capacity within a smaller footprint while maintaining reliable charge storage through distributed control mechanisms.
Solution Approach 2:
The memory device is divided into multiple independent memory cells, each with its own semiconductor column and gate electrode configuration. Each memory cell can be independently controlled and addressed, allowing selective operation of specific cells without affecting others. This segmentation enables scalable integration while maintaining operational reliability through isolated control of individual cells.
2Reliability
If gate electrodes are added to control channel regions, then charge storage reliability improves, but device complexity increases
Solution Approach 1:
The gate electrodes serve multiple functions: controlling channel regions for charge storage, enabling selective cell addressing, and facilitating read/write operations. The control gate electrodes positioned on opposite sides of semiconductor columns can independently control different channel regions, allowing a single structure to perform both storage and access control functions.
Solution Approach 2:
The patent combines multiple functional elements into integrated structures: gate electrodes are formed alongside semiconductor columns in a unified fabrication process, control circuits are integrated with memory cells, and multiple gate electrodes share common control lines. This merging reduces overall device complexity while achieving reliable charge storage through coordinated control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of charge storage and reduces voltage stress, enabling efficient data processing and storage in compact semiconductor devices while maintaining operational reliability.
Implementation Method 1
at least one tunneling insulation layer disposed between the second sidewall and the at least one charge storage layer
Implementation Method 2
at least one gate electrode and at least one control gate electrode disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column
Data Source
AI summary
A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at least one charge storage layer is disposed between the second sidewall and the at least one control gate electrode. The at least one gate electrode and the at least one control gate electrode may be disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column.