Columnar PLD Conversion Using ASIC Columns to Cut Die Size
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Solution Overview
Problem
Conventional field programmable gate arrays (FPGAs) face limitations in performance and cost compared to application-specific integrated circuits (ASICs), and their columnar architecture restricts input/output (I/O) circuit elements to a perimeter region, which can lead to inefficiencies in die size and customization.
Innovation Solution
The conversion of a columnar programmable logic device (PLD) to a columnar application-specific integrated circuit (ASIC)-like design by replacing configurable columns with application-specific circuitry, either by removing configuration memory cells and replacing them with hardwired connections or using ASIC core columns, allowing for optimized circuit design and reduced die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configurable columns are used in a columnar PLD, then adaptability and versatility are improved, but device complexity and die size increase
Solution Approach 1:
The PLD is divided into multiple columns, where each column can be independently configured or converted to application-specific circuitry. This segmentation allows selective hardening of specific columns rather than converting the entire device, thereby reducing overall die size while maintaining necessary adaptability in other columns.
Solution Approach 2:
Different columns within the same PLD can have different properties - some columns remain configurable while others are converted to fixed application-specific circuitry. This local differentiation optimizes the balance between adaptability and complexity by applying configurability only where needed.
2Speed
If configuration memory cells are removed and replaced with hardwired connections, then performance is improved, but ease of manufacture and reconfigurability worsen
Solution Approach 1:
The PLD structure allows dynamic conversion where columns can be configured during manufacturing or operation. Some columns maintain configuration memory cells for reconfigurability while others are hardwired for performance, creating a hybrid dynamic system that adapts to different operational requirements.
Solution Approach 2:
The conversion from configurable to application-specific circuitry can be performed as a preliminary action during the manufacturing process. Configuration memory cells are selectively removed or hardwired before the device is deployed, allowing performance optimization to be built-in from the start while retaining manufacturing flexibility through the selective conversion process.
3Device complexity
If I/O circuit elements are restricted to perimeter region, then device structure is simplified, but area utilization and productivity worsen
Solution Approach 1:
The columnar architecture introduces a vertical dimension to I/O placement, allowing I/O circuit elements to be distributed throughout the device height rather than being confined to the perimeter. This dimensional change enables better area utilization while maintaining structural organization through the columnar framework.
Solution Approach 2:
Columns in the columnar PLD serve multiple functions - they can contain logic elements, interconnect, and I/O circuitry within the same vertical structure. This multi-functionality allows I/O elements to be placed in interior columns rather than仅限于 perimeter, improving area utilization while maintaining structural simplicity through the universal column design.
Data Source
AI summary
A columnar programmable logic device (PLD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PLD having a columnar architecture associated with the columnar PLD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PLD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PLD design to the columnar ASIC-like design.