Columnar Semiconductor Storage Device Coupling Ratio
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Solution Overview
Problem
Conventional three-dimensionally-stacked semiconductor storage devices face increased costs and challenges in improving the coupling ratio between the charge storage layer and the control gate electrode, leading to inefficiencies in power consumption, operation speed, and erasing efficiency due to the complexity of the three-dimensional structure and manufacturing processes.
Innovation Solution
The semiconductor storage device configuration includes a columnar semiconductor with a tunnel dielectric film, a floating gate electrode, a block dielectric film, and control gate electrodes arranged to surround the floating gate electrode, improving the coupling ratio and reducing manufacturing complexity by using polycrystalline silicon and silicon oxide films, which allows for reduced power consumption and enhanced erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally stacked to improve integration density, then integration density is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacking architecture, where multiple memory cell layers are vertically arranged. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, allowing memory cells to be stacked in multiple layers rather than occupying only a single plane.
Solution Approach 2:
The patent implements a nested structure where control gate electrodes and charge storage layers are positioned within and around columnar semiconductor regions. The control gate electrodes surround the charge storage layers in a concentric arrangement, creating a nested configuration that maximizes spatial utilization and improves coupling efficiency within the three-dimensional memory cell structure.
2Manufacturing precision
If conventional photolithography and etching processes are performed for each layer, then manufacturing precision is maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple manufacturing steps into integrated processes. Specifically, the tunnel dielectric film formation, charge storage layer deposition, and control gate electrode patterning are performed in an integrated sequence using chemical vapor deposition and selective etching, rather than treating each layer as a separate manufacturing cycle. This merging reduces the total number of photolithography and etching operations required.
Solution Approach 2:
The patent performs preliminary formation of the tunnel dielectric film on the columnar semiconductor regions before depositing the charge storage layer material. This preliminary action establishes the dielectric foundation that enables subsequent charge storage layer formation and control gate electrode patterning, streamlining the overall manufacturing sequence by preparing surfaces in advance rather than performing separate operations for each layer.
3Shape
If charge storage layer is formed around columnar semiconductor layer, then three-dimensional structure is achieved, but coupling ratio between charge storage layer and control gate electrode deteriorates
Solution Approach 1:
The patent applies different materials and structures to different regions of the memory cell to optimize local coupling characteristics. The control gate electrodes are positioned in direct contact with or immediately adjacent to the charge storage layers in specific regions, creating localized high-coupling zones. The tunnel dielectric film is selectively formed only in regions where charge storage is required, maintaining strong coupling where needed while allowing structural variation elsewhere.
Solution Approach 2:
The patent employs asymmetric positioning of control gate electrodes relative to the columnar semiconductor structure. Rather than uniform symmetric arrangement, the control gate electrodes are strategically positioned to maximize coupling with the charge storage layers, with different electrode configurations at different heights and positions within the three-dimensional structure, optimizing the coupling ratio through asymmetric design.
Data Source
AI summary
According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.